Merge remote-tracking branch 'origin/main' into update-nixeda-patch

.github/test_sets/test_sets.yml

@@ -16,6 +16,8 @@
     - io_placer
     - test_sram_macro
     - manual_macro_placement_test
+    - name: non_const_async_reset
+      config_file: config.yaml
     - name: aes_user_project_wrapper
       test_name: aes_upw_new
       config_file: config.json

Changelog.md

@@ -14,37 +14,44 @@
 ## Documentation
 -->
 
-# 2.3.4
+# 2.3.5
 
 ## Tool Updates
 
 * `nix-eda` updated to 2.1.2
   * Pulls in a Python overlay fix and a fix for `gdstk`.
 
+# 2.3.4
+
+## Tool Updates
+
+* Added patch to Yosys to resolve an early return issue that broke non-const
+  asynchronous resets. See https://github.com/YosysHQ/yosys/issues/4712 for more
+  info.
+
 # 2.3.3
 
 ## Steps
 
 * `OpenROAD.Floorplan`
 
-  * Fixed an issue in `FP_SIZING`: `absolute` mode where if the die area's
-    x0 > x1 or y0 > y1, the computed core area would no longer fit in the die
-    area. Not that we recommend you ever do that, but technically OpenROAD
-    allows it.
+  * Fixed an issue in `FP_SIZING`: `absolute` mode where if the die area's x0 >
+    x1 or y0 > y1, the computed core area would no longer fit in the die area.
+    Not that we recommend you ever do that, but technically OpenROAD allows it.
 
 # 2.3.2
 
 ## Steps
 
 * `Yosys.*`
-  * Fixed blackbox Verilog and lib models causing a crash if they are
-    gzipped and/or have the extension `.gz`.
-    
+  * Fixed blackbox Verilog and lib models causing a crash if they are gzipped
+    and/or have the extension `.gz`.
+
 ## Tool Updates
 
 * Relaxed requirement on `httpx` to include `0.28.X`, which has no removals
   compared to `0.27.0`.
-  
+
 ## Documentation
 
 * Clarified support for gzipped files in the Classic flow.

flake.nix

@@ -59,6 +59,11 @@
           klayout = (pkgs.klayout.overrideAttrs(old: {
             configurePhase = builtins.replaceStrings ["-without-qtbinding"] ["-with-qtbinding"] old.configurePhase;
           }));
+          yosys = pkgs.yosys.overrideAttrs(old: {
+            patches = old.patches ++ [
+              ./nix/patches/yosys/async_rules.patch
+            ];
+          });
         })
         (
           pkgs': pkgs: let

nix/patches/yosys/async_rules.patch

@@ -0,0 +1,33 @@
+commit 626dbbe1e053071cf70890dd6592f461ae7eaacb
+Author: George Rennie <[email protected]>
+Date:   Thu Nov 7 00:06:03 2024 +0100
+
+    proc_dff: fix early return bug
+
+    * early return caused proc_dff to stop considering rules after seeing
+      one async rule - this is because continue should have been used to
+      continue to procecssing the next rule instead of returning from the
+      function
+
+diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
+index 3aad9ac1c..d094abf1b 100644
+--- a/passes/proc/proc_dff.cc
++++ b/passes/proc/proc_dff.cc
+@@ -262,7 +262,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
+ 		{
+ 			log_warning("Complex async reset for dff `%s'.\n", log_signal(sig));
+ 			gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, async_rules, proc);
+-			return;
++			continue;
+ 		}
+
+ 		// If there is a reset condition in the async rules, use it
+@@ -277,7 +277,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
+ 					sync_edge->type == RTLIL::SyncType::STp,
+ 					sync_level && sync_level->type == RTLIL::SyncType::ST1,
+ 					sync_edge->signal, sync_level->signal, proc);
+-			return;
++			continue;
+ 		}
+
+ 		gen_dff(mod, insig, rstval.as_const(), sig_q,

pyproject.toml

@@ -1,6 +1,6 @@
 [tool.poetry]
 name = "openlane"
-version = "2.3.4"
+version = "2.3.5"
 description = "An infrastructure for implementing chip design flows"
 authors = ["Efabless Corporation and Contributors <[email protected]>"]
 readme = "Readme.md"