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changes needed to add frigate to the flow
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@M0stafaRady
M0stafaRady committed Feb 11, 2025
1 parent dbb4263 commit 057786c
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Showing 4 changed files with 136 additions and 80 deletions.
137 changes: 88 additions & 49 deletions cocotb/caravel_cocotb/scripts/verify_cocotb/RunFlow.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -88,23 +88,13 @@ def set_tag(self):
self.logger.info(f"Run tag: {self.args.tag} ")

def set_paths(self, design_info):
if not os.path.exists(design_info["CARAVEL_ROOT"]) or not os.path.exists(
design_info["MCW_ROOT"]
):
raise NotADirectoryError(
f"CARAVEL_ROOT or MCW_ROOT not a correct directory CARAVEL_ROOT:{design_info['CARAVEL_ROOT']} MCW_ROOT:{design_info['MCW_ROOT']}"
)
if self.args.check_commits:
GitRepoChecker(
design_info["CARAVEL_ROOT"]
) # check repo synced with last commit
GitRepoChecker(
design_info["MCW_ROOT"]
) # check repo synced with last commit
if not os.path.exists(f'{design_info["PDK_ROOT"]}/{design_info["PDK"]}'):
raise NotADirectoryError(
f"PDK_ROOT/PDK is not a directory PDK_ROOT:{design_info['PDK_ROOT']}/{design_info['PDK']}"
)
RUN_PATH = self.args.run_path
SIM_PATH = (
f"{RUN_PATH}/sim"
if self.args.sim_path is None
else f"{self.args.sim_path}/sim"
)
VERILOG_PATH = f"{design_info['MCW_ROOT']}/verilog"
if not os.path.exists(design_info["USER_PROJECT_ROOT"]):
raise NotADirectoryError(
f"USER_PROJECT_ROOT is not a directory USER_PROJECT_ROOT:{design_info['USER_PROJECT_ROOT']}"
Expand All @@ -114,36 +104,76 @@ def set_paths(self, design_info):
GitRepoChecker(
design_info["USER_PROJECT_ROOT"]
) # check repo synced with last commit
Paths = namedtuple(
"Paths",
"CARAVEL_ROOT MCW_ROOT PDK_ROOT PDK CARAVEL_VERILOG_PATH VERILOG_PATH CARAVEL_PATH FIRMWARE_PATH RUN_PATH USER_PROJECT_ROOT SIM_PATH",
)
CARAVEL_VERILOG_PATH = f"{design_info['CARAVEL_ROOT']}/verilog"
VERILOG_PATH = f"{design_info['MCW_ROOT']}/verilog"
CARAVEL_PATH = f"{CARAVEL_VERILOG_PATH}"
if not os.path.exists(f'{design_info["PDK_ROOT"]}/{design_info["PDK"]}'):
raise NotADirectoryError(
f"PDK_ROOT/PDK is not a directory PDK_ROOT:{design_info['PDK_ROOT']}/{design_info['PDK']}"
)
if os.path.exists(f"{design_info['MCW_ROOT']}/verilog/dv/fw"):
FIRMWARE_PATH = f"{design_info['MCW_ROOT']}/verilog/dv/fw"
else:
FIRMWARE_PATH = f"{design_info['MCW_ROOT']}/verilog/dv/firmware"
RUN_PATH = self.args.run_path
SIM_PATH = (
f"{RUN_PATH}/sim"
if self.args.sim_path is None
else f"{self.args.sim_path}/sim"
)
self.paths = Paths(
design_info["CARAVEL_ROOT"],
design_info["MCW_ROOT"],
design_info["PDK_ROOT"],
design_info["PDK"],
CARAVEL_VERILOG_PATH,
VERILOG_PATH,
CARAVEL_PATH,
FIRMWARE_PATH,
RUN_PATH,
design_info["USER_PROJECT_ROOT"],
SIM_PATH,
)

if "CARAVEL_ROOT" in design_info:
if not os.path.exists(design_info["CARAVEL_ROOT"]) or not os.path.exists(
design_info["MCW_ROOT"]
):
raise NotADirectoryError(
f"CARAVEL_ROOT or MCW_ROOT not a correct directory CARAVEL_ROOT:{design_info['CARAVEL_ROOT']} MCW_ROOT:{design_info['MCW_ROOT']}"
)
if self.args.check_commits:
GitRepoChecker(
design_info["CARAVEL_ROOT"]
) # check repo synced with last commit
GitRepoChecker(
design_info["MCW_ROOT"]
) # check repo synced with last commit
Paths = namedtuple(
"Paths",
"CARAVEL_ROOT MCW_ROOT PDK_ROOT PDK CARAVEL_VERILOG_PATH VERILOG_PATH CARAVEL_PATH FIRMWARE_PATH RUN_PATH USER_PROJECT_ROOT SIM_PATH",
)
CARAVEL_VERILOG_PATH = f"{design_info['CARAVEL_ROOT']}/verilog"
CARAVEL_PATH = f"{CARAVEL_VERILOG_PATH}"
self.paths = Paths(
design_info["CARAVEL_ROOT"],
design_info["MCW_ROOT"],
design_info["PDK_ROOT"],
design_info["PDK"],
CARAVEL_VERILOG_PATH,
VERILOG_PATH,
CARAVEL_PATH,
FIRMWARE_PATH,
RUN_PATH,
design_info["USER_PROJECT_ROOT"],
SIM_PATH,
)
elif "FRIGATE_ROOT" in design_info:
Paths = namedtuple(
"Paths",
"FRIGATE_ROOT MCW_ROOT PDK_ROOT PDK RUN_PATH VERILOG_PATH FIRMWARE_PATH USER_PROJECT_ROOT SIM_PATH",
)
if not os.path.exists(design_info["FRIGATE_ROOT"]):
raise NotADirectoryError(
f"FRIGATE_ROOT is not a correct directory FRIGATE_ROOT:{design_info['FRIGATE_ROOT']}"
)
if not os.path.exists(design_info["MCW_ROOT"]):
raise NotADirectoryError(
f"MCW_ROOT is not a correct directory MCW_ROOT:{design_info['MCW_ROOT']}"
)
self.paths = Paths(
design_info["FRIGATE_ROOT"],
design_info["MCW_ROOT"],
design_info["PDK_ROOT"],
design_info["PDK"],
RUN_PATH,
VERILOG_PATH,
FIRMWARE_PATH,
design_info["USER_PROJECT_ROOT"],
SIM_PATH,
)





def set_cpu_type(self):
def_h_file = f"{self.paths.FIRMWARE_PATH}/defs.h"
Expand Down Expand Up @@ -208,13 +238,22 @@ def set_config_script(self, design_info):
design_configs = dict(
clock=self.args.clk, max_err=self.args.maxerr, PDK=self.args.pdk
)
design_configs.update(
dict(
CARAVEL_ROOT=self.paths.CARAVEL_ROOT,
MCW_ROOT=self.paths.MCW_ROOT,
PDK_ROOT=f'{self.paths.PDK_ROOT}/{design_info["PDK"]}',
if "CARAVEL_ROOT" in self.paths._fields:
design_configs.update(
dict(
CARAVEL_ROOT=self.paths.CARAVEL_ROOT,
MCW_ROOT=self.paths.MCW_ROOT,
PDK_ROOT=f'{self.paths.PDK_ROOT}/{design_info["PDK"]}',
)
)
elif "FRIGATE_ROOT" in self.paths._fields:
design_configs.update(
dict(
FRIGATE_ROOT=self.paths.FRIGATE_ROOT,
MCW_ROOT=self.paths.MCW_ROOT,
PDK_ROOT=f'{self.paths.PDK_ROOT}/{design_info["PDK"]}',
)
)
)
with open(new_config_path, "w") as file:
yaml.dump(design_configs, file)

Expand Down
17 changes: 10 additions & 7 deletions cocotb/caravel_cocotb/scripts/verify_cocotb/RunRegression.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -47,10 +47,13 @@ def set_common_macros(self):
paths_macros = [
f'RUN_PATH=\\"{self.paths.RUN_PATH}\\"',
f'TAG=\\"{self.args.tag}\\"',
f'CARAVEL_ROOT=\\"{self.paths.CARAVEL_ROOT}\\"',
f'MCW_ROOT=\\"{self.paths.MCW_ROOT}\\"',
f'USER_PROJECT_ROOT=\\"{self.paths.USER_PROJECT_ROOT}\\"',
]
if "CARAVEL_ROOT" in self.paths._fields:
paths_macros += [f'CARAVEL_ROOT=\\"{self.paths.CARAVEL_ROOT}\\"']
elif "FRIGATE_ROOT" in self.paths._fields:
paths_macros += [f'FRIGATE_ROOT=\\"{self.paths.FRIGATE_ROOT}\\"']

paths_macros.append(f'SIM_PATH=\\"{self.paths.SIM_PATH}/\\"')
if self.args.pdk != "gf180":
Expand Down Expand Up @@ -327,21 +330,22 @@ def write_git_log(self):
file_name = f"{self.paths.SIM_PATH}/{self.args.tag}/repos_info.log"
f = open(file_name, "w")
f.write(f"{'#'*4} Caravel repo info {'#'*4}\n")
url = "https://github.com/" + f"{run(f'cd {self.paths.CARAVEL_ROOT};git ls-remote --get-url', stdout=PIPE, stderr=PIPE, universal_newlines=True, shell=True).stdout}".replace(
ROOT_REPO = self.paths.CARAVEL_ROOT if "CARAVEL_ROOT" in self.paths._fields else self.paths.FRIGATE_ROOT if "FRIGATE_ROOT" in self.paths._fields else None
url = "https://github.com/" + f"{run(f'cd {ROOT_REPO};git ls-remote --get-url', stdout=PIPE, stderr=PIPE, universal_newlines=True, shell=True).stdout}".replace(
"[email protected]:", ""
).replace(
".git", ""
)
repo = f"Repo: {run(f'cd {self.paths.CARAVEL_ROOT};basename -s .git `git config --get remote.origin.url`', stdout=PIPE, stderr=PIPE, universal_newlines=True, shell=True).stdout} ({url})".replace(
repo = f"Repo: {run(f'cd {ROOT_REPO};basename -s .git `git config --get remote.origin.url`', stdout=PIPE, stderr=PIPE, universal_newlines=True, shell=True).stdout} ({url})".replace(
"\n", " "
)
f.write(f"{repo}\n")
f.write(
f"Branch name: {run(f'cd {self.paths.CARAVEL_ROOT};git symbolic-ref --short HEAD', stdout=PIPE, stderr=PIPE, universal_newlines=True, shell=True).stdout}"
f"Branch name: {run(f'cd {ROOT_REPO};git symbolic-ref --short HEAD', stdout=PIPE, stderr=PIPE, universal_newlines=True, shell=True).stdout}"
)
f.write(
run(
f"cd {self.paths.CARAVEL_ROOT};git show --quiet HEAD",
f"cd {ROOT_REPO};git show --quiet HEAD",
stdout=PIPE,
stderr=PIPE,
universal_newlines=True,
Expand Down Expand Up @@ -490,9 +494,8 @@ def unzip_sdf_files(self):
elif self.args.sim != "GL_SDF":
return
# keep caravel sdf dir
sdf_dir = f"{self.paths.CARAVEL_ROOT}/signoff/{'caravan' if self.args.caravan else 'caravel'}/primetime/sdf"
if self.args.sdfs_dir is None:
pass
sdf_dir = f"{self.paths.CARAVEL_ROOT}/signoff/{'caravan' if self.args.caravan else 'caravel'}/primetime/sdf"
else:
sdf_dir = self.args.sdfs_dir
if isinstance(sdf_dir, list):
Expand Down
12 changes: 10 additions & 2 deletions cocotb/caravel_cocotb/scripts/verify_cocotb/RunTest.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,16 @@ def hex_riscv_command_gen(self):
LINKER_SCRIPT = f"-Wl,-Bstatic,-T,{self.test.linker_script_file},--strip-debug "
CPUFLAGS = "-O2 -g -march=rv32i_zicsr -mabi=ilp32 -D__vexriscv__ -ffreestanding -nostdlib"
# CPUFLAGS = "-O2 -g -march=rv32imc_zicsr -mabi=ilp32 -D__vexriscv__ -ffreestanding -nostdlib"
includes = [
f"-I{ip}" for ip in self.get_ips_fw()
] + [
f"-I{self.paths.FIRMWARE_PATH}",
f"-I{self.paths.FIRMWARE_PATH}/APIs",
f"-I{self.paths.USER_PROJECT_ROOT}/verilog/dv/cocotb",
f"-I{self.paths.VERILOG_PATH}/dv/generated",
f"-I{self.paths.VERILOG_PATH}/dv/",
f"-I{self.paths.VERILOG_PATH}/common/",
]
includes = f" -I{self.paths.FIRMWARE_PATH} -I{self.paths.FIRMWARE_PATH}/APIs -I{self.paths.VERILOG_PATH}/dv/generated -I{self.paths.VERILOG_PATH}/dv/ -I{self.paths.VERILOG_PATH}/common"
includes += f" -I{self.paths.USER_PROJECT_ROOT}/verilog/dv/cocotb {' '.join([f'-I{ip}' for ip in self.get_ips_fw()])}"
elf_command = (
Expand Down Expand Up @@ -238,8 +248,6 @@ def _iverilog_docker_command_str(self, command=""):

def find_symbolic_links(self, directory):
sym_links = []
if not os.path.exists(directory):
return sym_links
for root, dirs, files in os.walk(directory):
for dir_name in dirs:
dir_path = os.path.join(root, dir_name)
Expand Down
50 changes: 28 additions & 22 deletions cocotb/caravel_cocotb/scripts/verify_cocotb/Test.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -78,10 +78,11 @@ def set_test_macros(self):
) # using debug register in this test isn't needed

def set_user_project(self):
project = "caravel" if "CARAVEL_ROOT" in self.paths._fields else "frigate" if "FRIGATE_ROOT" in self.paths._fields else None
if self.sim == "RTL":
user_include = f"{self.paths.USER_PROJECT_ROOT}/verilog/includes/includes.rtl.caravel_user_project"
user_include = f"{self.paths.USER_PROJECT_ROOT}/verilog/includes/includes.rtl.{project}_user_project"
else:
user_include = f"{self.paths.USER_PROJECT_ROOT}/verilog/includes/includes.gl.caravel_user_project"
user_include = f"{self.paths.USER_PROJECT_ROOT}/verilog/includes/includes.gl.{project}_user_project"
user_project = f" -f {user_include}"
self.write_includes_file(user_include)
return user_project.replace("\n", "")
Expand Down Expand Up @@ -212,9 +213,14 @@ def set_rerun_script(self):
"replace by cocotb path", self.paths.RUN_PATH
)
rerun_script = rerun_script.replace("replace by mgmt Root", self.paths.MCW_ROOT)
rerun_script = rerun_script.replace(
"replace by caravel Root", self.paths.CARAVEL_ROOT
)
if "CARAVEL_ROOT" in self.paths._fields:
rerun_script = rerun_script.replace(
"replace by caravel Root", self.paths.CARAVEL_ROOT
)
elif "FRIGATE_ROOT" in self.paths._fields:
rerun_script = rerun_script.replace(
"replace by caravel Root", self.paths.FRIGATE_ROOT
)
rerun_script = rerun_script.replace(
"replace by orignal rerun script", f"{self.test_dir}/rerun.py"
)
Expand Down Expand Up @@ -280,35 +286,32 @@ def write_includes_file(self, file):
paths = self.convert_list_to_include(file)
# write to include file in the top of the file
self.includes_file = f"{self.compilation_dir}/includes.v"
if self.sim == "RTL":
includes = self.convert_list_to_include(
f"{self.paths.VERILOG_PATH}/includes/includes.rtl.caravel"
)
elif self.sim == "GL_SDF":
self.sim_to_include = {
"RTL": "rtl",
"GL_SDF": "gl+sdf",
"GL": "gl",
}
if "CARAVEL_ROOT" in self.paths._fields: # when caravel include file from caravel mgmt
includes = self.convert_list_to_include(
f"{self.paths.VERILOG_PATH}/includes/includes.gl+sdf.caravel"
f"{self.paths.VERILOG_PATH}/includes/includes.{self.sim_to_include[self.sim]}.caravel"
)
elif self.sim == "GL":
elif "FRIGATE_ROOT" in self.paths._fields: # when caravel include file from frigate
includes = self.convert_list_to_include(
f"{self.paths.VERILOG_PATH}/includes/includes.gl.caravel"
f"{self.paths.FRIGATE_ROOT}/verilog/includes/includes.{self.sim_to_include[self.sim]}.frigate"
)
includes = paths + includes
open(self.includes_file, "w").write(includes)
move_defines_to_start(self.includes_file, 'defines.v"')
# copy includes used also
paths = open(file, "r").read()
self.includes_list = f"{self.compilation_dir}/includes"
if self.sim == "RTL":
includes = open(
f"{self.paths.VERILOG_PATH}/includes/includes.rtl.caravel", "r"
).read()
elif self.sim == "GL_SDF":
if "CARAVEL_ROOT" in self.paths._fields: # when caravel include file from caravel mgmt
includes = open(
f"{self.paths.VERILOG_PATH}/includes/includes.gl+sdf.caravel", "r"
f"{self.paths.VERILOG_PATH}/includes/includes.{self.sim_to_include[self.sim]}.caravel", "r"
).read()
elif self.sim == "GL":
elif "FRIGATE_ROOT" in self.paths._fields: # when caravel include file from frigate
includes = open(
f"{self.paths.VERILOG_PATH}/includes/includes.gl.caravel", "r"
f"{self.paths.FRIGATE_ROOT}/verilog/includes/includes.{self.sim_to_include[self.sim]}.frigate", "r"
).read()
includes = paths + includes
open(self.includes_list, "w").write(includes)
Expand All @@ -324,7 +327,10 @@ def convert_list_to_include(self, file):
if line and not line.startswith("#"):
# Replace $(VERILOG_PATH) with actual path
line = line.replace("$(VERILOG_PATH)", self.paths.VERILOG_PATH)
line = line.replace("$(CARAVEL_PATH)", self.paths.CARAVEL_PATH)
if "CARAVEL_ROOT" in self.paths._fields:
line = line.replace("$(CARAVEL_PATH)", self.paths.CARAVEL_PATH)
elif "FRIGATE_ROOT" in self.paths._fields:
line = line.replace("$(FRIGATE_VERILOG)", f"{self.paths.FRIGATE_ROOT}/verilog")
line = line.replace(
"$(USER_PROJECT_VERILOG)",
f"{self.paths.USER_PROJECT_ROOT}/verilog",
Expand Down

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