ece385_cpu-mp

Systemverilog implementation of single cycle LC-3 isa targeting altera de-10 lite development kit. details included in lab report

Name		Name	Last commit message	Last commit date
Latest commit History 37 Commits
db		db
devkits		devkits
greybox_tmp		greybox_tmp
incremental_db		incremental_db
lab5report		lab5report
output_files		output_files
simulation/modelsim		simulation/modelsim
.gitignore		.gitignore
DE10_LITE_Golden_Top.v		DE10_LITE_Golden_Top.v
HexDriver.sv		HexDriver.sv
ISDU.sv		ISDU.sv
Instantiateram.sv		Instantiateram.sv
Mem2IO.sv		Mem2IO.sv
README.md		README.md
SLC3_2.sv		SLC3_2.sv
alu.sv		alu.sv
datapath.sv		datapath.sv
ece385lab5.qpf		ece385lab5.qpf
ece385lab5.qsf		ece385lab5.qsf
ece385lab5_assignment_defaults.qdf		ece385lab5_assignment_defaults.qdf
memory_contents.sv		memory_contents.sv
multiplexer.sv		multiplexer.sv
qar_info.json		qar_info.json
ram.qip		ram.qip
ram.v		ram.v
ram_bb.v		ram_bb.v
register.sv		register.sv
slc3.sv		slc3.sv
slc3_sramtop.sv		slc3_sramtop.sv
slc3_testtop.sv		slc3_testtop.sv
synchronizers.sv		synchronizers.sv
test_memory.sv		test_memory.sv
testbench.sv		testbench.sv

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