Add ARM64 encodings for group IF_SVE_CC,CD#99284
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch Issue DetailsAdd encodings for the Matching capstone output: Contributing towards #94549
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@a74nh @kunalspathak @dotnet/arm64-contrib |
| INS_OPTS_SCALABLE_D); // INSR <Zdn>.<T>, <V><m> | ||
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| // IF_SVE_CD_2A | ||
| theEmitter->emitIns_R_R(INS_sve_insr, EA_SCALABLE, REG_V4, REG_R23, |
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As per Insr, this also takes ZR register. Can you please add a test for that?
| case IF_SVE_CD_2A: // ........xx...... ......mmmmmddddd -- SVE insert general register | ||
| assert(insOptsScalable(id->idInsOpt())); | ||
| assert(isVectorRegister(id->idReg1())); // ddddd | ||
| assert(isGeneralRegister(id->idReg2())); // mmmmm |
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| assert(isGeneralRegister(id->idReg2())); // mmmmm | |
| assert(isGeneralRegisterOrZR(id->idReg2())); // mmmmm |
| "q30", "q31" | ||
| }; | ||
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| static const char * const dRegNames[] = |
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these are already aliased at
runtime/src/coreclr/jit/registerarm64.h
Line 64 in fb700b3
| // Return value: | ||
| // A string that represents a SIMD scalar register name. | ||
| // | ||
| const char* emitter::emitSimdScalarRegName(regNumber reg, emitAttr attr) |
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| { | ||
| fmt = IF_SVE_CC_2A; | ||
| } | ||
| else if (isGeneralRegister(reg2)) |
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| else if (isGeneralRegister(reg2)) | |
| else if (isGeneralRegisterOrZR(reg2)) |
| //------------------------------------------------------------------------ | ||
| // emitDispScalarReg: Display a the name of a scalar mode of a vector register | ||
| // | ||
| void emitter::emitDispScalarReg(regNumber reg, insOpts opt, bool addComma) |
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pretty sure there is an existing method that does this.
| case IF_SVE_CD_2A: // ........xx...... ......mmmmmddddd -- SVE insert general register | ||
| assert(insOptsScalable(id->idInsOpt())); | ||
| assert(isVectorRegister(id->idReg1())); // ddddd | ||
| assert(isGeneralRegister(id->idReg2())); // mmmmm |
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For SVE_CD_2A , we should also assert the "width specifier" ( field)
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I'm not sure I can assert this one because it is not passed in as an argument, it is derived from the SVE size. But I have also noticed that it is currently accepting Q size which is invalid and I need to fix this.
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i think you should be able to do isValidVectorElemsizeFloat(elemsize)
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elemsize can be any of the standard four B,H,S,D sizes (as shown in the <T> table). The same size field is then reused for the general purpose register, as W or X, with W taking up 3 of the values (as shown in the <R> table).
So as long as we assert the B,H,S,D, then the W,X doesn't need checking.
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Add encodings for the
insrinstruction.Matching capstone output:
Contributing towards #94549