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Merged
merged 4 commits into from
Nov 23, 2023
Merged

Arm64/SVE: Add insEncodeReg* methods #95105

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bd97913
Add insEncodeReg* methods
kunalspathak Nov 22, 2023
ec4b465
Adjust the `ins` for sve instruction
kunalspathak Nov 22, 2023
dd24bb7
Update the comments
kunalspathak Nov 22, 2023
b1c0f4f
Use sve_ins_offset
kunalspathak Nov 22, 2023
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270 changes: 233 additions & 37 deletions src/coreclr/jit/emitarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3768,60 +3768,61 @@ emitter::code_t emitter::emitInsCodeSve(instruction ins, insFormat fmt)
}

assert(encoding_found);
const unsigned sve_ins_offset = ((unsigned)ins - INS_sve_invalid);

switch (index)
{
case 0:
assert(ins < ArrLen(insCodes1));
code = insCodes1[ins];
assert(sve_ins_offset < ArrLen(insCodes1));
code = insCodes1[sve_ins_offset];
break;
case 1:
assert(ins < ArrLen(insCodes2));
code = insCodes2[ins];
assert(sve_ins_offset < ArrLen(insCodes2));
code = insCodes2[sve_ins_offset];
break;
case 2:
assert(ins < ArrLen(insCodes3));
code = insCodes3[ins];
assert(sve_ins_offset < ArrLen(insCodes3));
code = insCodes3[sve_ins_offset];
break;
case 3:
assert(ins < ArrLen(insCodes4));
code = insCodes4[ins];
assert(sve_ins_offset < ArrLen(insCodes4));
code = insCodes4[sve_ins_offset];
break;
case 4:
assert(ins < ArrLen(insCodes5));
code = insCodes5[ins];
assert(sve_ins_offset < ArrLen(insCodes5));
code = insCodes5[sve_ins_offset];
break;
case 5:
assert(ins < ArrLen(insCodes6));
code = insCodes6[ins];
assert(sve_ins_offset < ArrLen(insCodes6));
code = insCodes6[sve_ins_offset];
break;
case 6:
assert(ins < ArrLen(insCodes7));
code = insCodes7[ins];
assert(sve_ins_offset < ArrLen(insCodes7));
code = insCodes7[sve_ins_offset];
break;
case 7:
assert(ins < ArrLen(insCodes8));
code = insCodes8[ins];
assert(sve_ins_offset < ArrLen(insCodes8));
code = insCodes8[sve_ins_offset];
break;
case 8:
assert(ins < ArrLen(insCodes9));
code = insCodes9[ins];
assert(sve_ins_offset < ArrLen(insCodes9));
code = insCodes9[sve_ins_offset];
break;
case 9:
assert(ins < ArrLen(insCodes10));
code = insCodes10[ins];
assert(sve_ins_offset < ArrLen(insCodes10));
code = insCodes10[sve_ins_offset];
break;
case 10:
assert(ins < ArrLen(insCodes11));
code = insCodes11[ins];
assert(sve_ins_offset < ArrLen(insCodes11));
code = insCodes11[sve_ins_offset];
break;
case 11:
assert(ins < ArrLen(insCodes12));
code = insCodes12[ins];
assert(sve_ins_offset < ArrLen(insCodes12));
code = insCodes12[sve_ins_offset];
break;
case 12:
assert(ins < ArrLen(insCodes13));
code = insCodes13[ins];
assert(sve_ins_offset < ArrLen(insCodes13));
code = insCodes13[sve_ins_offset];
break;
}

Expand Down Expand Up @@ -10633,41 +10634,236 @@ void emitter::emitIns_Call(EmitCallType callType,

/*****************************************************************************
*
* Returns an encoding for the specified register used in the 'Pd' position
* Return an encoding for the specified 'V' register used in '4' thru '0' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_V_4_to_0(regNumber reg)
{
assert(isVectorRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0;
assert((ureg >= 0) && (ureg <= 32));
return ureg << 0;
}

/*****************************************************************************
*
* Return an encoding for the specified 'V' register used in '9' thru '5' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_Pd(regNumber reg)
/*static*/ emitter::code_t emitter::insEncodeReg_V_9_to_5(regNumber reg)
{
assert(emitter::isPredicateRegister(reg));
assert(isVectorRegister(reg));
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I want to change this to insEncodeReg_V_9_to_5(regNumber reg, int lowbit, int highbit)
But your way is safer.

At the risk of making more hard to parse macros:

#define insEncodeFunc(highbit, lowbit) emitter::code_t emitter::insEncodeReg_V_#highbit_to_#lowbit(regNumber reg) /
{ /
    emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0; /
    assert((ureg >= 0) && (ureg <= 32)); /
    return ureg << 5; /
} /

insEncodeFunc(9, 5);
insEncodeFunc(12, 10);
etc

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@BruceForstall - any preference? if we don't want to use macro, we can also convert in a function that takes lowbit as a parameter.

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For some of the predicate ones, I've had to change them to assert(isLowPredicateRegister(reg)); because they only have 4 bits, as opposed to 5 bits.

So, maybe better leaving as functions.

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I'd prefer functions, even if they are quite duplicative. Makes for easier debugging. Sounds like @a74nh already found reasons the asserts would be different.

emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0;
assert((ureg >= 0) && (ureg <= 32));
return ureg << 5;
}

/*****************************************************************************
*
* Return an encoding for the specified 'P' register used in '12' thru '10' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_P_12_to_10(regNumber reg)
{
assert(isPredicateRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_P0;
assert((ureg >= 0) && (ureg <= 15));
return ureg;
return ureg << 10;
}

/*****************************************************************************
*
* Return an encoding for the specified 'V' register used in '21' thru '17' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_V_21_to_17(regNumber reg)
{
assert(isVectorRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0;
assert((ureg >= 0) && (ureg <= 32));
return ureg << 17;
}

/*****************************************************************************
*
* Return an encoding for the specified 'R' register used in '21' thru '17' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_R_21_to_17(regNumber reg)
{
assert(isIntegerRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg;
assert((ureg >= 0) && (ureg <= 32));
return ureg << 17;
}

/*****************************************************************************
*
* Return an encoding for the specified 'R' register used in '9' thru '5' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_R_9_to_5(regNumber reg)
{
assert(isIntegerRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg;
assert((ureg >= 0) && (ureg <= 32));
return ureg << 5;
}

/*****************************************************************************
*
* Return an encoding for the specified 'R' register used in '4' thru '0' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_R_4_to_0(regNumber reg)
{
assert(isIntegerRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg;
assert((ureg >= 0) && (ureg <= 32));
return ureg << 0;
}

/*****************************************************************************
*
* Return an encoding for the specified 'P' register used in '20' thru '17' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_P_20_to_17(regNumber reg)
{
assert(isPredicateRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_P0;
assert((ureg >= 0) && (ureg <= 15));
return ureg << 17;
}

/*****************************************************************************
*
* Returns an encoding for the specified register used in the 'Pn' position
* Return an encoding for the specified 'P' register used in '3' thru '0' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_Pn(regNumber reg)
/*static*/ emitter::code_t emitter::insEncodeReg_P_3_to_0(regNumber reg)
{
assert(emitter::isPredicateRegister(reg));
assert(isPredicateRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_P0;
assert((ureg >= 0) && (ureg <= 15));
return ureg << 0;
}

/*****************************************************************************
*
* Return an encoding for the specified 'P' register used in '8' thru '5' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_P_8_to_5(regNumber reg)
{
assert(isPredicateRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_P0;
assert((ureg >= 0) && (ureg <= 15));
return ureg << 5;
}

/*****************************************************************************
*
* Returns an encoding for the specified register used in the 'Pm' position
* Return an encoding for the specified 'P' register used in '13' thru '10' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_Pm(regNumber reg)
/*static*/ emitter::code_t emitter::insEncodeReg_P_13_to_10(regNumber reg)
{
assert(emitter::isPredicateRegister(reg));
assert(isPredicateRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_P0;
assert((ureg >= 0) && (ureg <= 15));
return ureg << 16;
return ureg << 10;
}

/*****************************************************************************
*
* Return an encoding for the specified 'R' register used in '18' thru '17' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_R_18_to_17(regNumber reg)
{
assert(isIntegerRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg;
assert((ureg >= 0) && (ureg <= 32));
return ureg << 17;
}

/*****************************************************************************
*
* Return an encoding for the specified 'P' register used in '7' thru '5' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_P_7_to_5(regNumber reg)
{
assert(isPredicateRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_P0;
assert((ureg >= 0) && (ureg <= 15));
return ureg << 5;
}

/*****************************************************************************
*
* Return an encoding for the specified 'P' register used in '3' thru '1' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_P_3_to_1(regNumber reg)
{
assert(isPredicateRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_P0;
assert((ureg >= 0) && (ureg <= 15));
return ureg << 1;
}

/*****************************************************************************
*
* Return an encoding for the specified 'P' register used in '2' thru '0' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_P_2_to_0(regNumber reg)
{
assert(isPredicateRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_P0;
assert((ureg >= 0) && (ureg <= 15));
return ureg << 0;
}

/*****************************************************************************
*
* Return an encoding for the specified 'V' register used in '19' thru '17' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_V_19_to_17(regNumber reg)
{
assert(isVectorRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0;
assert((ureg >= 0) && (ureg <= 32));
return ureg << 17;
}

/*****************************************************************************
*
* Return an encoding for the specified 'V' register used in '20' thru '17' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_V_20_to_17(regNumber reg)
{
assert(isVectorRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0;
assert((ureg >= 0) && (ureg <= 32));
return ureg << 17;
}

/*****************************************************************************
*
* Return an encoding for the specified 'V' register used in '9' thru '6' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_V_9_to_6(regNumber reg)
{
assert(isVectorRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0;
assert((ureg >= 0) && (ureg <= 32));
return ureg << 6;
}

/*****************************************************************************
Expand Down
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