Verilog: allow vector-typed operands to edge event control

regression/verilog/synthesis/posedge_vector.desc

@@ -1,8 +1,8 @@
 CORE
 posedge_vector.v
 --module main
-^file posedge_vector.v line \d+: pos/negedge expected to have Boolean as operand, but got \[7:0\]$
-^EXIT=2$
+^no properties$
+^EXIT=10$
 ^SIGNAL=0$
 --
 ^warning: ignoring

regression/verilog/synthesis/posedge_vector.v

@@ -1,5 +1,6 @@
 module main(input [7:0] data);
 
+  // Allowed; only the LSB will be considered.
   always @(posedge data);
 
 endmodule

src/verilog/verilog_synthesis.cpp

@@ -2729,22 +2729,6 @@ void verilog_synthesist::synth_event_guard(
           << "pos/negedge expected to have one operand";
       }
 
-      if(to_unary_expr(*it).op().id() != ID_symbol)
-      {
-        throw errort().with_location(it->source_location())
-          << "pos/negedge expected to have symbol as operand, "
-             "but got " +
-               to_unary_expr(*it).op().pretty();
-      }
-
-      if(to_unary_expr(*it).op().type().id() != ID_bool)
-      {
-        throw errort().with_location(it->source_location())
-          << "pos/negedge expected to have Boolean as operand, "
-             "but got " +
-               to_string(to_unary_expr(*it).op().type());
-      }
-
       irep_idt identifier="conf::clock_enable_mode";
 
       // check symbol_table for clock guard
@@ -2753,7 +2737,15 @@ void verilog_synthesist::synth_event_guard(
       {
         // found! we make it a guard
 
-        guards.push_back(to_unary_expr(*it).op());
+        auto &op = to_unary_expr(*it).op();
+
+        if(op.type().id() == ID_bool)
+          guards.push_back(op);
+        else
+        {
+          // get LSB
+          guards.push_back(extractbit_exprt{op, integer_typet{}.zero_expr()});
+        }
 
         throw errort() << "Notice: using clock guard " << identifier;
       }