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Verilog: KNOWNBUG test for property ... endproperty #932

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Verilog: KNOWNBUG test for property ... endproperty
The type checker uses the wrong fragement of the expression syntax for
property ...  endproperty.

Replicates #931.
kroening committed Jan 16, 2025
commit b395a5e5facc0325638db2ce60ab3e757ce61dda
File renamed without changes.
File renamed without changes.
11 changes: 11 additions & 0 deletions regression/verilog/property/named_property2.desc
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
KNOWNBUG
named_property2.sv
--bound 20
^\[main\.assert\.1\] always main\.x_is_eventually_ten: PROVED up to bound 20$
^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
The type checker only allows expressions, not properties in property ...
endproperty.
12 changes: 12 additions & 0 deletions regression/verilog/property/named_property2.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
module main(input clk);

reg [31:0] x = 0;
always_ff @(posedge clk) x++;

property x_is_eventually_ten;
s_eventually x == 10
endproperty : x_is_eventually_ten

assert property (x_is_eventually_ten);

endmodule