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SystemVerilog: type parameter ports #842

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SystemVerilog: type parameter ports #842

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3 changes: 1 addition & 2 deletions regression/verilog/modules/parameter_ports4.desc
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Original file line number Diff line number Diff line change
@@ -1,8 +1,7 @@
KNOWNBUG
CORE
parameter_ports4.sv
--bound 0
^EXIT=0$
^SIGNAL=0$
--
--
The type parameter port needs to be parsed as a type.
10 changes: 8 additions & 2 deletions src/verilog/parser.y
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Original file line number Diff line number Diff line change
Expand Up @@ -1763,11 +1763,15 @@ list_of_variable_identifiers:
parameter_port_declaration:
TOK_PARAMETER data_type_or_implicit param_assignment
{ $$ = $3; }
| TOK_PARAMETER TOK_TYPE data_type_or_implicit param_assignment
{ $$ = $4; }
| TOK_LOCALPARAM data_type_or_implicit param_assignment
{ $$ = $3; }
| data_type param_assignment
{ $$ = $2; }
| param_assignment
| TOK_TYPE param_assignment
{ $$ = $2; }
;

list_of_defparam_assignments:
Expand All @@ -1789,13 +1793,15 @@ list_of_param_assignments:
{ $$=$1; mto($$, $3); }
;

param_assignment: param_identifier '=' constant_param_expression
param_assignment:
param_identifier '=' constant_param_expression
{ init($$, ID_parameter);
auto base_name = stack_expr($1).id();
stack_expr($$).set(ID_identifier, base_name);
stack_expr($$).set(ID_base_name, base_name);
addswap($$, ID_value, $3); }
;
| type_assignment
;

list_of_type_assignments:
type_assignment
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