SystemVerilog: chandle data type

CHANGELOG

@@ -6,6 +6,7 @@
 * Verilog: fix for nor/nand/xnor primitive gates
 * SystemVerilog: $bitstoreal/$bitstoshortreal, $realtobits/$shortrealtobits
 * SystemVerilog: $itor, $rtoi
+* SystemVerilog: chandle
 
 # EBMC 5.4
 

regression/verilog/data-types/chandle1.desc

@@ -0,0 +1,8 @@
+CORE
+chandle1.sv
+--bound 0
+^\[main\.p0\] always main\.some_handle == null: PROVED up to bound 0$
+^\[main\.p1\] always \$typename\(main\.some_handle\) == "chandle": PROVED up to bound 0$
+^EXIT=0$
+^SIGNAL=0$
+--

regression/verilog/data-types/chandle1.sv

@@ -0,0 +1,9 @@
+module main;
+
+  // IEEE 1800-2017 6.14
+  chandle some_handle = null;
+
+  p0: assert final (some_handle == null);
+  p1: assert final ($typename(some_handle) == "chandle");
+
+endmodule

src/hw_cbmc_irep_ids.h

@@ -104,7 +104,8 @@ IREP_ID_ONE(verilog_value_range)
 IREP_ID_ONE(verilog_void)
 IREP_ID_ONE(verilog_streaming_concatenation_left_to_right)
 IREP_ID_ONE(verilog_streaming_concatenation_right_to_left)
-IREP_ID_ONE(chandle)
+IREP_ID_ONE(verilog_chandle)
+IREP_ID_ONE(verilog_null)
 IREP_ID_ONE(event)
 IREP_ID_ONE(reg)
 IREP_ID_ONE(macromodule)

src/verilog/Makefile

@@ -26,6 +26,7 @@ SRC = aval_bval_encoding.cpp \
       verilog_typecheck_base.cpp \
       verilog_typecheck_expr.cpp \
       verilog_typecheck_sva.cpp \
+      verilog_types.cpp \
       verilog_y.tab.cpp \
       vtype.cpp
 

src/verilog/expr2verilog.cpp

@@ -1260,6 +1260,15 @@ expr2verilogt::resultt expr2verilogt::convert_constant(
 
     dest += '"';
   }
+  else if(type.id() == ID_verilog_chandle)
+  {
+    if(src.get_value() == ID_NULL)
+    {
+      dest = "null";
+    }
+    else
+      return convert_norep(src, precedence);
+  }
   else
     return convert_norep(src, precedence);
 
@@ -2030,6 +2039,8 @@ std::string expr2verilogt::convert(const typet &type)
 
     return dest;
   }
+  else if(type.id() == ID_verilog_chandle)
+    return "chandle";
   else if(type.id() == ID_verilog_genvar)
     return "genvar";
   else if(type.id()==ID_integer)
@@ -2040,6 +2051,8 @@ std::string expr2verilogt::convert(const typet &type)
     return "real";
   else if(type.id()==ID_verilog_realtime)
     return "realtime";
+  else if(type.id() == ID_verilog_null)
+    return "null";
   else if(type.id() == ID_verilog_enum)
   {
     return "enum";

src/verilog/parser.y

@@ -1477,7 +1477,7 @@ data_type:
 	| TOK_STRING
 	        { init($$, ID_string); }
 	| TOK_CHANDLE
-	        { init($$, ID_chandle); }
+	        { init($$, ID_verilog_chandle); }
 	| TOK_VIRTUAL interface_opt interface_identifier
 	        { init($$, "virtual_interface"); }
 	| /*scope_opt*/ type_identifier packed_dimension_brace
@@ -4039,7 +4039,7 @@ primary:  primary_literal
 	| cast
 	| assignment_pattern_expression
 	| streaming_concatenation
-        | TOK_NULL { init($$, ID_NULL); }
+        | TOK_NULL { init($$, ID_verilog_null); }
         | TOK_THIS { init($$, ID_this); }
 	;
 

src/verilog/verilog_elaborate_type.cpp

@@ -383,6 +383,10 @@ typet verilog_typecheck_exprt::elaborate_type(const typet &src)
   {
     return src;
   }
+  else if(src.id() == ID_verilog_chandle)
+  {
+    return src;
+  }
   else
   {
     throw errort().with_location(source_location)

src/verilog/verilog_lowering.cpp

@@ -19,6 +19,7 @@ Author: Daniel Kroening, [email protected]
 #include "convert_literals.h"
 #include "verilog_bits.h"
 #include "verilog_expr.h"
+#include "verilog_types.h"
 
 /// Lowers
 /// * the three Verilog real types to floatbv;
@@ -42,6 +43,10 @@ typet verilog_lowering(typet type)
   {
     return lower_to_aval_bval(type);
   }
+  else if(type.id() == ID_verilog_chandle)
+  {
+    return to_verilog_chandle_type(type).encoding();
+  }
   else
     return type;
 }
@@ -347,9 +352,26 @@ exprt verilog_lowering(exprt expr)
       result.add_source_location() = expr.source_location();
       expr = std::move(result);
     }
+    else if(expr.type().id() == ID_verilog_chandle)
+    {
+      // this is 'null'
+      return to_verilog_chandle_type(expr.type()).null_expr();
+    }
 
     return expr;
   }
+  else if(expr.id() == ID_symbol)
+  {
+    auto &symbol_expr = to_symbol_expr(expr);
+    if(expr.type().id() == ID_verilog_chandle)
+    {
+      auto &chandle_type = to_verilog_chandle_type(expr.type());
+      return symbol_exprt{
+        symbol_expr.get_identifier(), chandle_type.encoding()};
+    }
+    else
+      return expr;
+  }
   else if(expr.id() == ID_concatenation)
   {
     if(

src/verilog/verilog_synthesis.cpp

@@ -3346,7 +3346,12 @@ void verilog_synthesist::synth_assignments(
   if(!symbol.is_state_var)
     post_process_wire(symbol.name, new_value);
 
-  equal_exprt equality_expr{symbol_expr(symbol, curr_or_next), new_value};
+  auto lhs = symbol_expr(symbol, curr_or_next);
+
+  DATA_INVARIANT(
+    lhs.type() == new_value.type(), "synth_assignments type consistency");
+
+  equal_exprt equality_expr{std::move(lhs), new_value};
 
   constraints.add_to_operands(std::move(equality_expr));
 }

src/verilog/verilog_typecheck_expr.cpp

@@ -753,6 +753,10 @@ exprt verilog_typecheck_exprt::typename_string(const exprt &expr)
   {
     s = "shortreal";
   }
+  else if(type.id() == ID_verilog_chandle)
+  {
+    s = "chandle";
+  }
   else
     s = "?";
 
@@ -1107,6 +1111,11 @@ exprt verilog_typecheck_exprt::convert_nullary_expr(nullary_exprt expr)
     throw errort().with_location(expr.source_location())
       << "'this' outside of method";
   }
+  else if(expr.id() == ID_verilog_null)
+  {
+    return constant_exprt{ID_NULL, typet{ID_verilog_null}}.with_source_location(
+      expr.source_location());
+  }
   else
   {
     throw errort().with_location(expr.source_location())
@@ -2041,6 +2050,17 @@ void verilog_typecheck_exprt::implicit_typecast(
       return;
     }
   }
+  else if(src_type.id() == ID_verilog_null)
+  {
+    if(dest_type.id() == ID_verilog_chandle)
+    {
+      if(expr.id() == ID_constant)
+      {
+        expr.type() = dest_type;
+        return;
+      }
+    }
+  }
 
   throw errort().with_location(expr.source_location())
     << "failed to convert `" << to_string(src_type) << "' to `"
@@ -2293,6 +2313,12 @@ typet verilog_typecheck_exprt::max_type(
   vtypet vt0=vtypet(t0);
   vtypet vt1=vtypet(t1);
 
+  if(vt0.is_null() || vt1.is_chandle())
+    return t1;
+
+  if(vt0.is_chandle() || vt1.is_null())
+    return t0;
+
   if(vt0.is_other() || vt1.is_other())
     return static_cast<const typet &>(get_nil_irep());
 

src/verilog/verilog_types.cpp

@@ -0,0 +1,16 @@
+/*******************************************************************\
+
+Module: Verilog Types
+
+Author: Daniel Kroening, [email protected]
+
+\*******************************************************************/
+
+#include "verilog_types.h"
+
+#include <util/std_expr.h>
+
+constant_exprt verilog_chandle_typet::null_expr() const
+{
+  return encoding().all_zeros_expr();
+}

src/verilog/verilog_types.h

@@ -544,4 +544,41 @@ inline verilog_union_typet &to_verilog_union_type(typet &type)
   return static_cast<verilog_union_typet &>(type);
 }
 
+/// a pointer type
+class verilog_chandle_typet : public typet
+{
+public:
+  inline verilog_chandle_typet() : typet(ID_verilog_chandle)
+  {
+  }
+
+  bv_typet encoding() const
+  {
+    return bv_typet{32};
+  }
+
+  constant_exprt null_expr() const;
+};
+
+/// \brief Cast a typet to a \ref verilog_chandle_typet
+///
+/// This is an unchecked conversion. \a type must be known to be \ref
+/// verilog_chandle_typet. Will fail with a precondition violation if type
+/// doesn't match.
+///
+/// \param type: Source type.
+/// \return Object of type \ref verilog_chandle_typet
+inline const verilog_chandle_typet &to_verilog_chandle_type(const typet &type)
+{
+  PRECONDITION(type.id() == ID_verilog_chandle);
+  return static_cast<const verilog_chandle_typet &>(type);
+}
+
+/// \copydoc to_chandle_type(const typet &)
+inline verilog_chandle_typet &to_verilog_chandle_type(typet &type)
+{
+  PRECONDITION(type.id() == ID_verilog_chandle);
+  return static_cast<verilog_chandle_typet &>(type);
+}
+
 #endif

src/verilog/vtype.cpp

@@ -73,6 +73,11 @@ vtypet::vtypet(const typet &type)
     vtype = VERILOG_REAL;
     width = 32;
   }
+  else if(type.id() == ID_verilog_chandle)
+  {
+    vtype = CHANDLE;
+    width = 32;
+  }
   else 
   {
     width=0;
@@ -117,6 +122,12 @@ std::ostream &operator << (std::ostream &out, const vtypet &vtype)
   case vtypet::VERILOG_REAL:
     return out << "real";
 
+  case vtypet::CHANDLE:
+    return out << "chandle";
+
+  case vtypet::NULL_TYPE:
+    return out << "null";
+
   case vtypet::UNKNOWN:
   case vtypet::OTHER:
   default:

src/verilog/vtype.h

@@ -31,6 +31,14 @@ class vtypet
   {
     return vtype == VERILOG_REAL;
   }
+  bool is_chandle() const
+  {
+    return vtype == CHANDLE;
+  }
+  bool is_null() const
+  {
+    return vtype == NULL_TYPE;
+  }
   inline bool is_other() const { return vtype==OTHER; }
 
 protected:
@@ -44,6 +52,8 @@ class vtypet
     VERILOG_SIGNED,
     VERILOG_UNSIGNED,
     VERILOG_REAL,
+    CHANDLE,
+    NULL_TYPE,
     OTHER
   } _vtypet;
   _vtypet vtype;