SystemVerilog: chandle data type
#837
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kroening
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kroening
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The first commit here is #846, which is still marked as draft. So I’m not entirely sure whether this is one is ready? |
It's good to go -- there'll be more types added to the type lowering. |
tautschnig
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Jan 3, 2025
src/verilog/verilog_synthesis.cpp
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| if(lhs.type() != new_value.type()) | ||
| throw errort() << lhs.pretty() << "\nVS\n" << new_value.pretty(); | ||
| DATA_INVARIANT( | ||
| lhs.type() == new_value.type(), "synth_assignments type consistency"); |
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Why do we have the trivially-satisfied DATA_INVARIANT on this occasion (when we otherwise don't seem to do that)?
kroening
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This one now requires resolving conflicts. |
This adds 1800 2017 6.14 chandle.
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This adds 1800 2017 6.14
chandle.