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Merge pull request #578 from diffblue/assignment_pattern
Verilog: assignment pattern expressions
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CORE | ||
array_literal1.sv | ||
--bound 0 | ||
^EXIT=0$ | ||
^SIGNAL=0$ | ||
-- |
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module main; | ||
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reg [7:0] my_array[10] = '{1, 2, 3, 4, 5, 6, 7, 8, 9, 10}; | ||
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initial p0: assert property (my_array[0] == 1); | ||
initial p1: assert property (my_array[9] == 10); | ||
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endmodule |
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CORE | ||
array_literal2.sv | ||
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^file array_literal2\.sv line 3: number of expressions does not match number of array elements$ | ||
^CONVERSION ERROR$ | ||
^EXIT=2$ | ||
^SIGNAL=0$ | ||
-- |
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module main; | ||
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reg [7:0] my_array[10] = '{1, 2, 3, 4}; // too short | ||
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endmodule |
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CORE | ||
structs5.sv | ||
--bound 0 | ||
^\[main\.p1\] always main\.s\.field1 == 1: PROVED up to bound 0$ | ||
^\[main\.p2\] always main\.s\.field2 == 0: PROVED up to bound 0$ | ||
^\[main\.p3\] always main\.s\.field3 == 115: PROVED up to bound 0$ | ||
^EXIT=0$ | ||
^SIGNAL=0$ | ||
-- |
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module main; | ||
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struct packed { | ||
bit field1, field2; | ||
bit [6:0] field3; | ||
} s = '{ 1, 0, 'b1110011 }; | ||
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// Expected to pass. | ||
p1: assert property (s.field1 == 1); | ||
p2: assert property (s.field2 == 0); | ||
p3: assert property (s.field3 == 'b1110011); | ||
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endmodule |
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