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Merge pull request #579 from diffblue/named_property1
SystemVerilog: named properties
2 parents 21146f9 + 94604a9 commit e746526

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10 files changed

+144
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10 files changed

+144
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lines changed

‎regression/verilog/SVA/named_property1.desc

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@@ -0,0 +1,9 @@
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CORE
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named_property1.sv
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--bound 0
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^\[main\.assert\.1\] always main\.x == 10: PROVED up to bound 0$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--

‎regression/verilog/SVA/named_property1.sv

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@@ -0,0 +1,11 @@
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module main;
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wire [31:0] x = 10;
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property x_is_ten;
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x == 10
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endproperty : x_is_ten
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assert property (x_is_ten);
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endmodule

‎src/hw_cbmc_irep_ids.h

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@@ -60,6 +60,7 @@ IREP_ID_ONE(verilog_non_indexed_part_select)
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IREP_ID_ONE(verilog_indexed_part_select_plus)
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IREP_ID_ONE(verilog_indexed_part_select_minus)
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IREP_ID_ONE(verilog_past)
63+
IREP_ID_ONE(verilog_property_declaration)
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IREP_ID_ONE(chandle)
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IREP_ID_ONE(event)
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IREP_ID_ONE(reg)

‎src/verilog/parser.y

Lines changed: 34 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2039,9 +2039,42 @@ assertion_item_declaration:
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;
20402040

20412041
property_declaration:
2042-
TOK_PROPERTY property_identifier TOK_ENDPROPERTY
2042+
TOK_PROPERTY property_identifier property_port_list_paren_opt ';'
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property_spec
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TOK_ENDPROPERTY property_identifier_opt
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{ init($$, ID_verilog_property_declaration);
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stack_expr($$).set(ID_base_name, stack_expr($2).id());
2047+
mto($$, $5); }
20432048
;
20442049

2050+
property_identifier_opt:
2051+
/* optional */
2052+
| TOK_COLON property_identifier
2053+
;
2054+
2055+
property_port_list_paren_opt:
2056+
/* optional */
2057+
| '(' property_port_list_opt ')'
2058+
;
2059+
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property_port_list_opt:
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/* optional */
2062+
| property_port_list
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;
2064+
2065+
property_port_list:
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property_port_item
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| property_port_list_opt ',' property_port_item
2068+
;
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property_port_item:
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attribute_instance_brace property_formal_type formal_port_identifier variable_dimension_brace
2072+
;
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property_formal_type:
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TOK_PROPERTY
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;
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property_spec:
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TOK_DISABLE TOK_IFF '(' expression ')' property_expr
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{ $$=$6; }

‎src/verilog/verilog_elaborate.cpp

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Original file line numberDiff line numberDiff line change
@@ -113,6 +113,11 @@ void verilog_typecheckt::collect_symbols(
113113
}
114114
}
115115

116+
void verilog_typecheckt::collect_symbols(
117+
const verilog_property_declarationt &declaration)
118+
{
119+
}
120+
116121
void verilog_typecheckt::collect_symbols(const typet &type)
117122
{
118123
// These types are not yet converted.
@@ -800,6 +805,10 @@ void verilog_typecheckt::collect_symbols(
800805
else if(module_item.id() == ID_verilog_covergroup)
801806
{
802807
}
808+
else if(module_item.id() == ID_verilog_property_declaration)
809+
{
810+
collect_symbols(to_verilog_property_declaration(module_item));
811+
}
803812
else
804813
DATA_INVARIANT(false, "unexpected module item: " + module_item.id_string());
805814
}

‎src/verilog/verilog_expr.h

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Original file line numberDiff line numberDiff line change
@@ -2123,4 +2123,37 @@ to_verilog_indexed_part_select_plus_or_minus_expr(exprt &expr)
21232123
return static_cast<verilog_indexed_part_select_plus_or_minus_exprt &>(expr);
21242124
}
21252125

2126+
class verilog_property_declarationt : public verilog_module_itemt
2127+
{
2128+
public:
2129+
const irep_idt &base_name() const
2130+
{
2131+
return get(ID_base_name);
2132+
}
2133+
2134+
const exprt &cond() const
2135+
{
2136+
return op0();
2137+
}
2138+
2139+
exprt &cond()
2140+
{
2141+
return op0();
2142+
}
2143+
};
2144+
2145+
inline const verilog_property_declarationt &
2146+
to_verilog_property_declaration(const exprt &expr)
2147+
{
2148+
PRECONDITION(expr.id() == ID_verilog_property_declaration);
2149+
return static_cast<const verilog_property_declarationt &>(expr);
2150+
}
2151+
2152+
inline verilog_property_declarationt &
2153+
to_verilog_property_declaration(exprt &expr)
2154+
{
2155+
PRECONDITION(expr.id() == ID_verilog_property_declaration);
2156+
return static_cast<verilog_property_declarationt &>(expr);
2157+
}
2158+
21262159
#endif

‎src/verilog/verilog_interfaces.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -299,6 +299,9 @@ void verilog_typecheckt::interface_module_item(
299299
else if(module_item.id() == ID_verilog_covergroup)
300300
{
301301
}
302+
else if(module_item.id() == ID_verilog_property_declaration)
303+
{
304+
}
302305
else
303306
{
304307
DATA_INVARIANT(false, "unexpected module item: " + module_item.id_string());

‎src/verilog/verilog_synthesis.cpp

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Original file line numberDiff line numberDiff line change
@@ -3231,6 +3231,9 @@ void verilog_synthesist::synth_module_item(
32313231
else if(module_item.id() == ID_verilog_covergroup)
32323232
{
32333233
}
3234+
else if(module_item.id() == ID_verilog_property_declaration)
3235+
{
3236+
}
32343237
else
32353238
{
32363239
throw errort().with_location(module_item.source_location())

‎src/verilog/verilog_typecheck.cpp

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Original file line numberDiff line numberDiff line change
@@ -1639,6 +1639,10 @@ void verilog_typecheckt::convert_module_item(
16391639
else if(module_item.id() == ID_verilog_covergroup)
16401640
{
16411641
}
1642+
else if(module_item.id() == ID_verilog_property_declaration)
1643+
{
1644+
convert_property_declaration(to_verilog_property_declaration(module_item));
1645+
}
16421646
else
16431647
{
16441648
throw errort().with_location(module_item.source_location())
@@ -1648,6 +1652,41 @@ void verilog_typecheckt::convert_module_item(
16481652

16491653
/*******************************************************************\
16501654
1655+
Function: verilog_typecheckt::convert_property_declaration
1656+
1657+
Inputs:
1658+
1659+
Outputs:
1660+
1661+
Purpose:
1662+
1663+
\*******************************************************************/
1664+
1665+
void verilog_typecheckt::convert_property_declaration(
1666+
verilog_property_declarationt &declaration)
1667+
{
1668+
auto base_name = declaration.base_name();
1669+
auto full_identifier = hierarchical_identifier(base_name);
1670+
1671+
convert_expr(declaration.cond());
1672+
make_boolean(declaration.cond());
1673+
1674+
auto type = bool_typet{};
1675+
type.set(ID_C_verilog_type, ID_verilog_property_declaration);
1676+
symbolt symbol{full_identifier, type, mode};
1677+
1678+
symbol.module = module_identifier;
1679+
symbol.base_name = base_name;
1680+
symbol.pretty_name = strip_verilog_prefix(symbol.name);
1681+
symbol.is_macro = true;
1682+
symbol.value = declaration.cond();
1683+
symbol.location = declaration.source_location();
1684+
1685+
add_symbol(std::move(symbol));
1686+
}
1687+
1688+
/*******************************************************************\
1689+
16511690
Function: verilog_typecheckt::convert_statements
16521691
16531692
Inputs:

‎src/verilog/verilog_typecheck.h

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Original file line numberDiff line numberDiff line change
@@ -92,6 +92,7 @@ class verilog_typecheckt:
9292
void collect_symbols(const verilog_declt &);
9393
void collect_symbols(const verilog_lett &);
9494
void collect_symbols(const verilog_statementt &);
95+
void collect_symbols(const verilog_property_declarationt &);
9596
void
9697
collect_symbols(const typet &, const verilog_parameter_declt::declaratort &);
9798
void collect_port_symbols(const verilog_declt &);
@@ -171,6 +172,7 @@ class verilog_typecheckt:
171172
void convert_assignments(exprt &trans);
172173
void convert_module_item(class verilog_module_itemt &);
173174
void convert_parameter_override(const class verilog_parameter_overridet &);
175+
void convert_property_declaration(class verilog_property_declarationt &);
174176

175177
void integer_expr(exprt &expr);
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