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Merge pull request #581 from diffblue/array_functions1
Verilog: `$low`, `$high`, `$increment`, `$left`, `$right`
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‎regression/verilog/system-functions/array_functions1.desc

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CORE
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array_functions1.sv
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--module main --bound 0
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^\[main\.pP0\] always 32 == 32 && 1 == 1: PROVED up to bound 0$
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^\[main\.pP1\] always 0 == 0 && 31 == 31: PROVED up to bound 0$
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^\[main\.pP2\] always 1 == 1 && 32 == 32: PROVED up to bound 0$
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^\[main\.pP3\] always 0 == 0 && 31 == 31: PROVED up to bound 0$
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^\[main\.pP4\] always 1 == 1: PROVED up to bound 0$
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^\[main\.pP5\] always -1 == -1: PROVED up to bound 0$
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^\[main\.pU0\] always 32 == 32 && 1 == 1: PROVED up to bound 0$
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^\[main\.pU1\] always 0 == 0 && 31 == 31: PROVED up to bound 0$
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^\[main\.pU2\] always 31 == 31 && 0 == 0: PROVED up to bound 0$
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^\[main\.pU3\] always 1 == 1 && 32 == 32: PROVED up to bound 0$
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^\[main\.pU4\] always 0 == 0 && 31 == 31: PROVED up to bound 0$
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^\[main\.pU5\] always 0 == 0 && 31 == 31: PROVED up to bound 0$
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^\[main\.pU6\] always 1 == 1: PROVED up to bound 0$
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^\[main\.pU7\] always -1 == -1: PROVED up to bound 0$
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^\[main\.pU8\] always 1 == 1: PROVED up to bound 0$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring

‎regression/verilog/system-functions/array_functions1.sv

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module main;
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wire [32:1] packed1;
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wire [0:31] packed2;
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wire unpacked1 [32:1];
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wire unpacked2 [0:31];
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wire unpacked3 [32];
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pP0: assert property ($left(packed1) == 32 and $right(packed1) == 1);
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pP1: assert property ($left(packed2) == 0 and $right(packed2) == 31);
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pP2: assert property ($low(packed1) == 1 and $high(packed1) == 32);
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pP3: assert property ($low(packed2) == 0 and $high(packed2) == 31);
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pP4: assert property ($increment(packed1) == 1);
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pP5: assert property ($increment(packed2) == -1);
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pU0: assert property ($left(unpacked1) == 32 and $right(unpacked1) == 1);
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pU1: assert property ($left(unpacked2) == 0 and $right(unpacked2) == 31);
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pU2: assert property ($left(unpacked3) == 31 and $right(unpacked3) == 0);
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pU3: assert property ($low(unpacked1) == 1 and $high(unpacked1) == 32);
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pU4: assert property ($low(unpacked2) == 0 and $high(unpacked2) == 31);
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pU5: assert property ($low(unpacked3) == 0 and $high(unpacked3) == 31);
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pU6: assert property ($increment(unpacked1) == 1);
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pU7: assert property ($increment(unpacked2) == -1);
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pU8: assert property ($increment(unpacked3) == 1);
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endmodule

‎src/verilog/verilog_typecheck_expr.cpp

Lines changed: 202 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -447,6 +447,179 @@ exprt verilog_typecheck_exprt::bits(const exprt &expr)
447447

448448
/*******************************************************************\
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Function: verilog_typecheck_exprt::left
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Inputs:
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Outputs:
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Purpose:
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\*******************************************************************/
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constant_exprt verilog_typecheck_exprt::left(const exprt &expr)
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{
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// unpacked array: left bound
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// packed array: index of most significant element
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// 0 otherwise
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auto left = [](const typet &type) -> mp_integer {
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if(
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type.id() == ID_unsignedbv || type.id() == ID_signedbv ||
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type.id() == ID_verilog_unsignedbv || type.id() == ID_verilog_signedbv ||
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type.id() == ID_bool)
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{
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auto offset = type.get_int(ID_C_offset);
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if(type.get_bool(ID_C_little_endian))
473+
return offset + get_width(type) - 1;
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else
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return offset;
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}
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else if(type.id() == ID_array)
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{
479+
auto offset = numeric_cast_v<mp_integer>(
480+
to_constant_expr(static_cast<const exprt &>(type.find(ID_offset))));
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if(type.get_bool(ID_C_little_endian))
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return offset +
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numeric_cast_v<mp_integer>(
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to_constant_expr(to_array_type(type).size())) -
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1;
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else
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return offset;
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}
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else
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return 0;
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};
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return from_integer(left(expr.type()), integer_typet{});
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}
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/*******************************************************************\
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Function: verilog_typecheck_exprt::right
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Inputs:
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Outputs:
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Purpose:
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\*******************************************************************/
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constant_exprt verilog_typecheck_exprt::right(const exprt &expr)
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{
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// unpacked array: right bound
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// packed array: index of least significant element
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// 0 otherwise
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auto right = [](const typet &type) -> mp_integer {
514+
if(
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type.id() == ID_unsignedbv || type.id() == ID_signedbv ||
516+
type.id() == ID_verilog_unsignedbv || type.id() == ID_verilog_signedbv ||
517+
type.id() == ID_bool)
518+
{
519+
auto offset = type.get_int(ID_C_offset);
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if(type.get_bool(ID_C_little_endian))
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return offset;
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else
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return offset + get_width(type) - 1;
524+
}
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else if(type.id() == ID_array)
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{
527+
auto offset = numeric_cast_v<mp_integer>(
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to_constant_expr(static_cast<const exprt &>(type.find(ID_offset))));
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if(type.get_bool(ID_C_little_endian))
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return offset;
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else
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return offset +
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numeric_cast_v<mp_integer>(
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to_constant_expr(to_array_type(type).size())) -
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1;
536+
}
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else
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return 0;
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};
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return from_integer(right(expr.type()), integer_typet{});
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}
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/*******************************************************************\
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Function: verilog_typecheck_exprt::increment
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Inputs:
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Outputs:
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Purpose:
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\*******************************************************************/
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constant_exprt verilog_typecheck_exprt::increment(const exprt &expr)
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{
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// fixed-size dimension: 1 if $left >= $right, -1 otherwise
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auto increment = [](const typet &type) -> mp_integer {
560+
if(
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type.id() == ID_unsignedbv || type.id() == ID_signedbv ||
562+
type.id() == ID_verilog_unsignedbv || type.id() == ID_verilog_signedbv ||
563+
type.id() == ID_array)
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{
565+
if(type.get_bool(ID_C_little_endian))
566+
return 1;
567+
else
568+
return -1;
569+
}
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else
571+
return -1;
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};
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return from_integer(increment(expr.type()), integer_typet{});
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}
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/*******************************************************************\
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Function: verilog_typecheck_exprt::low
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Inputs:
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Outputs:
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Purpose:
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\*******************************************************************/
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constant_exprt verilog_typecheck_exprt::low(const exprt &expr)
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{
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// $left if $increment returns –1
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// $right otherwise
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if(numeric_cast_v<mp_integer>(increment(expr)) == -1)
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return left(expr);
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else
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return right(expr);
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}
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/*******************************************************************\
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Function: verilog_typecheck_exprt::high
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Inputs:
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Outputs:
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Purpose:
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\*******************************************************************/
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constant_exprt verilog_typecheck_exprt::high(const exprt &expr)
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{
613+
// $right if $increment returns –1
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// $left otherwise
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if(numeric_cast_v<mp_integer>(increment(expr)) == -1)
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return right(expr);
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else
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return left(expr);
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}
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/*******************************************************************\
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450623
Function: verilog_typecheck_exprt::convert_system_function
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Inputs:
@@ -549,12 +722,14 @@ exprt verilog_typecheck_exprt::convert_system_function(
549722
expr.type() = arguments.front().type();
550723
return std::move(expr);
551724
}
552-
else if(identifier == "$bits")
725+
else if(
726+
identifier == "$bits" || identifier == "$left" || identifier == "$right" ||
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identifier == "$increment" || identifier == "$low" || identifier == "$high")
553728
{
554729
if(arguments.size() != 1)
555730
{
556731
throw errort().with_location(expr.source_location())
557-
<< "$bits takes one argument";
732+
<< identifier << " takes one argument";
558733
}
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560735
// The return type is integer.
@@ -1370,6 +1545,31 @@ exprt verilog_typecheck_exprt::elaborate_constant_system_function_call(
13701545
DATA_INVARIANT(arguments.size() == 1, "$bits has one argument");
13711546
return bits(arguments[0]);
13721547
}
1548+
else if(identifier == "$low")
1549+
{
1550+
DATA_INVARIANT(arguments.size() == 1, "$low has one argument");
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return low(arguments[0]);
1552+
}
1553+
else if(identifier == "$high")
1554+
{
1555+
DATA_INVARIANT(arguments.size() == 1, "$high has one argument");
1556+
return high(arguments[0]);
1557+
}
1558+
else if(identifier == "$left")
1559+
{
1560+
DATA_INVARIANT(arguments.size() == 1, "$left has one argument");
1561+
return left(arguments[0]);
1562+
}
1563+
else if(identifier == "$right")
1564+
{
1565+
DATA_INVARIANT(arguments.size() == 1, "$right has one argument");
1566+
return right(arguments[0]);
1567+
}
1568+
else if(identifier == "$increment")
1569+
{
1570+
DATA_INVARIANT(arguments.size() == 1, "$increment has one argument");
1571+
return increment(arguments[0]);
1572+
}
13731573
else if(identifier == "$clog2")
13741574
{
13751575
// the ceiling of the log with base 2 of the argument

‎src/verilog/verilog_typecheck_expr.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -133,8 +133,14 @@ class verilog_typecheck_exprt:public verilog_typecheck_baset
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void tc_binary_expr(const exprt &expr, exprt &op0, exprt &op1);
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void no_bool_ops(exprt &);
135135

136+
// system functions
136137
exprt bits(const exprt &);
137138
std::optional<mp_integer> bits_rec(const typet &) const;
139+
constant_exprt left(const exprt &);
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constant_exprt right(const exprt &);
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constant_exprt low(const exprt &);
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constant_exprt high(const exprt &);
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constant_exprt increment(const exprt &);
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};
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140146
bool verilog_typecheck(

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