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Verilog: KNOWNBUG test for task invocation without parentheses
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kroening committed Jan 24, 2025
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9 changes: 9 additions & 0 deletions regression/verilog/tasks/task_invocation1.desc
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KNOWNBUG
task_invocation1.sv

^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
The parser rejects invocations without ().
12 changes: 12 additions & 0 deletions regression/verilog/tasks/task_invocation1.sv
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module top(output reg [31:0] y);

task my_task;
y=123;
endtask

// the parentheses are optional
always_comb my_task;

assert final (y==123);

endmodule

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