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Merge pull request #945 from diffblue/clocking_declaration
SystemVerilog: clocking declarations
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CORE | ||
clocking1.sv | ||
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^no properties$ | ||
^EXIT=10$ | ||
^SIGNAL=0$ | ||
-- | ||
^warning: ignoring | ||
-- |
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Original file line number | Diff line number | Diff line change |
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module main(input clk); | ||
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clocking my_clocking @(posedge clk); | ||
endclocking | ||
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// The identifier is optional. | ||
default clocking @(posedge clk); | ||
endclocking | ||
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endmodule |
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