Merge pull request #75 from diffblue/verilog-preprocessor-define-arguments

Verilog preprocessor define arguments

Author: kroening

regression/verilog/preprocessor/define1.desc

@@ -0,0 +1,19 @@
+CORE
+define1.v
+--preprocess
+// Enable multi-line checking
+activate-multi-line-match
+`line 1 "define1.v" 0
+
+
+
+value
+
+value
+
+x-y-z
+x-y-value
+^EXIT=0$
+^SIGNAL=0$
+--
+^PREPROCESSING FAILED$

regression/verilog/preprocessor/define1.v

@@ -0,0 +1,9 @@
+`define basic
+`basic
+`define with_value value
+`with_value
+`define uses_previous `with_value
+`uses_previous
+`define with_parameter(a, b, c) a-b-c
+`with_parameter(x, y, z)
+`with_parameter(x, y, `with_value)