Verilog preprocessor: implement define parameters

This implements Verilog 2001 preprocessor defines with parameters.
diffblue · Sep 25, 2023 · 939dc0e · 939dc0e
1 parent b58ecea
commit 939dc0e
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Showing 4 changed files with 292 additions and 99 deletions.
diff --git a/regression/verilog/preprocessor/define1.desc b/regression/verilog/preprocessor/define1.desc
@@ -0,0 +1,19 @@
+CORE
+define1.v
+--preprocess
+// Enable multi-line checking
+activate-multi-line-match
+`line 1 "define1.v" 0
+
+
+
+value
+
+value
+
+x-y-z
+x-y-value
+^EXIT=0$
+^SIGNAL=0$
+--
+^PREPROCESSING FAILED$
diff --git a/regression/verilog/preprocessor/define1.v b/regression/verilog/preprocessor/define1.v
@@ -0,0 +1,9 @@
+`define basic
+`basic
+`define with_value value
+`with_value
+`define uses_previous `with_value
+`uses_previous
+`define with_parameter(a, b, c) a-b-c
+`with_parameter(x, y, z)
+`with_parameter(x, y, `with_value)