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Merge pull request #629 from diffblue/reduction1
Verilog: constant folding for reduction operators
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CORE broken-smt-backend | ||
reduction1.v | ||
--bound 0 | ||
^EXIT=0$ | ||
^SIGNAL=0$ | ||
-- | ||
^warning: ignoring |
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module main(input [31:0] in); | ||
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// reduction and | ||
always assert reduction_and1: | ||
&3'b111 == 1 && &3'b101 == 0; | ||
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// constant folding | ||
wire [&3'b111:0] wire_and; | ||
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// reduction nand | ||
always assert reduction_nand1: | ||
~&in == !(&in); | ||
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// constant folding | ||
wire [~&3'b111:0] wire_nand; | ||
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// reduction or | ||
always assert reduction_or1: | ||
|3'b000 == 0 && |3'b101 == 1; | ||
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// constant folding | ||
wire [|3'b101:0] wire_or; | ||
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// reduction nor | ||
always assert reduction_nor1: | ||
~|in == !(|in); | ||
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// constant folding | ||
wire [~|3'b000:0] wire_nor; | ||
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// reduction xor | ||
always assert reduction_xor1: | ||
^3'b000 == 0 && ^3'b111 == 1; | ||
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// constant folding | ||
wire [^3'b111:0] wire_xor; | ||
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// reduction xnor, variant 1 | ||
always assert reduction_xnor1: | ||
~^in == !(^in); | ||
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// constant folding | ||
wire [~^3'b000:0] wire_xnor1; | ||
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// reduction xnor, variant 2 | ||
always assert reduction_xnor2: | ||
^~in == !(^in); | ||
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// constant folding | ||
wire [^~3'b000:0] wire_xnor2; | ||
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endmodule |
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