Merge pull request #823 from diffblue/equality3

Verilog: KNOWNBUG tests for operand type errors

Author: tautschnig

regression/verilog/expressions/concatenation5.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+concatenation5.v
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This should be errored.

regression/verilog/expressions/concatenation5.v

@@ -0,0 +1,6 @@
+module main;
+
+  // {} only takes integral types
+  wire x = {1.1, 1.2};
+
+endmodule

regression/verilog/expressions/equality3.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+equality3.v
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This should be errored.

regression/verilog/expressions/equality3.v

@@ -0,0 +1,6 @@
+module main;
+
+  // === takes any type except real/shortreal
+  wire x = 1.1 === 1.2;
+
+endmodule

regression/verilog/expressions/mod2.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+mod2.v
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This should be errored.

regression/verilog/expressions/mod2.v

@@ -0,0 +1,6 @@
+module main;
+
+  // % only takes integral types
+  wire x = 1.1 % 1.2;
+
+endmodule

regression/verilog/expressions/shr2.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+shr2.v
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This should be errored.

regression/verilog/expressions/shr2.v

@@ -0,0 +1,6 @@
+module main;
+
+  // >> only takes integral types
+  wire x = 1.1 >> 1.2;
+
+endmodule

regression/verilog/expressions/wildcard_equality2.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+wildcard_equality2.v
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This should be errored.

regression/verilog/expressions/wildcard_equality2.v

@@ -0,0 +1,6 @@
+module main;
+
+  // ==? only takes integral types
+  wire x = 1.1 === 1.2;
+
+endmodule