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Merge pull request #820 from diffblue/verilog-tc-unary
Verilog: typechecking for remaining unary expressions
2 parents 87310da + 27474b3 commit 8444385

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+25
-4
lines changed

1 file changed

+25
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src/verilog/verilog_typecheck_expr.cpp

Lines changed: 25 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2606,16 +2606,37 @@ exprt verilog_typecheck_exprt::convert_unary_expr(unary_exprt expr)
26062606
expr.type() = expr.op().operands()[0].type();
26072607
return std::move(expr);
26082608
}
2609-
else
2609+
else if(expr.id() == ID_bitnot)
26102610
{
26112611
convert_expr(expr.op());
26122612
expr.type() = expr.op().type();
26132613

2614-
// check boolean operators
2615-
2616-
if(expr.type().id()==ID_bool && expr.id()==ID_bitnot)
2614+
// Boolean?
2615+
if(expr.type().id() == ID_bool)
26172616
expr.id(ID_not);
26182617
}
2618+
else if(expr.id() == ID_posedge || expr.id() == ID_negedge)
2619+
{
2620+
convert_expr(expr.op());
2621+
expr.type() = bool_typet{};
2622+
}
2623+
else if(expr.id() == ID_verilog_smv_eventually)
2624+
{
2625+
convert_expr(expr.op());
2626+
make_boolean(expr.op());
2627+
expr.type() = bool_typet{};
2628+
}
2629+
else if(
2630+
expr.id() == ID_postincrement || expr.id() == ID_preincrement ||
2631+
expr.id() == ID_postdecrement || expr.id() == ID_predecrement)
2632+
{
2633+
convert_expr(expr.op());
2634+
expr.type() = expr.op().type();
2635+
}
2636+
else
2637+
{
2638+
throw errort() << "no conversion for unary expression " << expr.id();
2639+
}
26192640

26202641
return std::move(expr);
26212642
}

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