Merge pull request #421 from diffblue/indexed-part-select

Verilog: indexed part select expressions

Author: tautschnig

regression/verilog/part-select/index-of-real.desc

@@ -0,0 +1,8 @@
+CORE
+index-of-real.sv
+
+^file .* line 5: bit-select of real is not allowed$
+^EXIT=2$
+^SIGNAL=0$
+--
+^warning: ignoring

regression/verilog/part-select/index-of-real.sv

@@ -0,0 +1,7 @@
+module main;
+
+  // 1800-2017 6.12.1
+  real some_real;
+  wire x = some_real[0];
+
+endmodule

regression/verilog/indexed-part-select1/test.desc renamed to regression/verilog/part-select/indexed-part-select1.desc

@@ -1,6 +1,6 @@
 CORE broken-smt-backend
-main.sv
---bound 1
+indexed-part-select1.sv
+--bound 0
 ^EXIT=0$
 ^SIGNAL=0$
 --

regression/verilog/indexed-part-select1/main.sv renamed to regression/verilog/part-select/indexed-part-select1.sv

@@ -9,7 +9,6 @@ module main(in);
     out[16 +: 16]=0;
   end
 
-  always assert property1:
-    { in, { 8 { 1'b0 }} } == out;
+  p1: assert property ({ in, { 8 { 1'b0 }} } == out);
 
 endmodule

regression/verilog/part-select/indexed-part-select2.desc

@@ -0,0 +1,8 @@
+CORE
+indexed-part-select2.sv
+
+^file .* line 4: expected constant expression, but got `main\.width'$
+^EXIT=2$
+^SIGNAL=0$
+--
+^warning: ignoring

regression/verilog/part-select/indexed-part-select2.sv

@@ -0,0 +1,6 @@
+module main(input [7:0] in, input [2:0] width);
+
+  // The width of an indexed part-select must be a constant
+  wire [7:0] out = in[0 +: width];
+
+endmodule

regression/verilog/part-select/indexed-part-select3.desc

@@ -0,0 +1,8 @@
+CORE
+indexed-part-select3.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--

regression/verilog/part-select/indexed-part-select3.sv

@@ -0,0 +1,9 @@
+module main(input [7:0] in, input [2:0] where);
+
+  // The base index of an indexed part-select
+  // does not need to be constant.
+  wire out = in[where +: 1];
+
+  p0: assert property (out == in[where]);
+
+endmodule

regression/verilog/part-select/part-select-of-real.desc

@@ -0,0 +1,8 @@
+CORE
+part-select-of-real.sv
+
+^file .* line 5: real not allowed in part select$
+^EXIT=2$
+^SIGNAL=0$
+--
+^warning: ignoring

regression/verilog/part-select/part-select-of-real.sv

@@ -0,0 +1,7 @@
+module main;
+
+  // 1800-2017 6.12.1
+  real some_real;
+  wire [7:0] x = some_real[7:0];
+
+endmodule