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Verilog: indexed part select expressions with non-constant index
This implements support for indexed part select expressions where the index is not an elaboration-time constant.
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CORE
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index-of-real.sv
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^file .* line 5: bit-select of real is not allowed$
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^EXIT=2$
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^SIGNAL=0$
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--
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^warning: ignoring
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module main;
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// 1800-2017 6.12.1
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real some_real;
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wire x = some_real[0];
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endmodule

regression/verilog/indexed-part-select1/test.desc renamed to regression/verilog/part-select/indexed-part-select1.desc

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CORE broken-smt-backend
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main.sv
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--bound 1
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indexed-part-select1.sv
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--bound 0
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^EXIT=0$
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^SIGNAL=0$
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--

regression/verilog/indexed-part-select1/main.sv renamed to regression/verilog/part-select/indexed-part-select1.sv

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out[16 +: 16]=0;
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end
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always assert property1:
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{ in, { 8 { 1'b0 }} } == out;
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p1: assert property ({ in, { 8 { 1'b0 }} } == out);
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endmodule
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CORE
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indexed-part-select2.sv
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^file .* line 4: expected constant expression, but got `main\.width'$
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^EXIT=2$
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^SIGNAL=0$
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--
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^warning: ignoring
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module main(input [7:0] in, input [2:0] width);
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// The width of an indexed part-select must be a constant
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wire [7:0] out = in[0 +: width];
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endmodule
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CORE
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indexed-part-select3.sv
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--bound 0
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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module main(input [7:0] in, input [2:0] where);
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// The base index of an indexed part-select
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// does not need to be constant.
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wire out = in[where +: 1];
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p0: assert property (out == in[where]);
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endmodule
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CORE
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part-select-of-real.sv
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^file .* line 5: real not allowed in part select$
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^EXIT=2$
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^SIGNAL=0$
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--
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^warning: ignoring
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module main;
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// 1800-2017 6.12.1
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real some_real;
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wire [7:0] x = some_real[7:0];
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endmodule

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