Verilog preprocessor: fix include buffering

To prevent scanning beyond an `include directive, we abort read-ahead
whenever we see a newline.

regression/verilog/preprocessor/include1.desc

@@ -0,0 +1,16 @@
+CORE
+include1.v
+--preprocess
+// Enable multi-line checking
+activate-multi-line-match
+`line 1 "include1.v" 0
+`line 1 "include1b.v" 1
+line b 1
+line b 2
+`line 1 "include1.v" 2
+
+line 2
+line 3
+^EXIT=0$
+^SIGNAL=0$
+--

regression/verilog/preprocessor/include1.v

@@ -0,0 +1,3 @@
+`include "include1b.v"
+line 2
+line 3

regression/verilog/preprocessor/include1b.v

@@ -0,0 +1,2 @@
+line b 1
+line b 2

src/verilog/verilog_preprocessor_tokenizer.cpp

@@ -88,13 +88,19 @@ verilog_preprocessor_tokenizert::verilog_preprocessor_tokenizert(
 std::size_t
 verilog_preprocessor_tokenizert::yy_input(char *buffer, std::size_t max_size)
 {
-  std::size_t result;
-  for(result = 0; result < max_size; result++)
+  std::size_t result = 0;
+  while(result < max_size)
   {
     char ch;
     if(!in.get(ch))
-      return result; // eof
-    buffer[result] = ch;
+      break; // eof
+    buffer[result++] = ch;
+    if(ch == '\n')
+    {
+      // We need to abort prematurely to enable
+      // switching input streams on `include.
+      break;
+    }
   }
   return result;
 }