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Verilog: consolidate expression-related tests in verilog/expressions
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kroening committed Jun 21, 2024
1 parent 6cc2ed2 commit 4bbab28
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CORE
main.v
constants1.v
--bound 1
^EXIT=0$
^SIGNAL=0$
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CORE
main.v
shr1.v
--bound 1
^EXIT=0$
^SIGNAL=0$
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