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added an option to conver a verilog description into a aiger file
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Original file line number | Diff line number | Diff line change |
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#include <iostream> | ||
#include <list> | ||
#include <vector> | ||
#include <queue> | ||
#include <set> | ||
#include <map> | ||
#include <stdio.h> | ||
#include <stdlib.h> | ||
#include <strings.h> | ||
#include <string.h> | ||
#include <time.h> | ||
#include <algorithm> | ||
#include <ctime> | ||
#include <climits> | ||
#include <cassert> | ||
#include <sys/time.h> | ||
#include <sys/resource.h> | ||
#include <unistd.h> | ||
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#include <ebmc/ebmc_base.h> | ||
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#include "minisat/core/Solver.h" | ||
#include "minisat/simp/SimpSolver.h" | ||
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using namespace std; | ||
#include "dnf_io.hh" | ||
#include "ccircuit.hh" | ||
#include "m0ic3.hh" | ||
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/*==================================== | ||
P R I N T _ A I G E R _ F O R M A T | ||
====================================*/ | ||
void CompInfo::print_aiger_format() | ||
{ | ||
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int num_consts; | ||
int num_buffs; | ||
check_circuit(num_buffs,num_consts); | ||
// printf("num_buffs = %d\n",num_buffs); | ||
assert(num_consts <= 2); | ||
string full_name; | ||
assert(strlen(out_file) > 0); | ||
full_name = out_file; | ||
full_name += ".aag"; | ||
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FILE *fp = fopen(full_name.c_str(),"w"); | ||
assert(fp!= NULL); | ||
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DNF Gates; | ||
int out_ind = form_aiger_gates(Gates); | ||
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int max_var = find_max_aiger_var(Gates); | ||
print_aiger_header(fp,max_var,Gates.size()); | ||
print_aiger_inps(fp); | ||
print_aiger_latches(fp); | ||
print_aiger_output(fp,Gates,out_ind); | ||
print_aiger_constrs(fp); | ||
print_aiger_gates(fp,Gates); | ||
fclose(fp); | ||
} /* end of function print_aiger_format */ | ||
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/*======================================= | ||
F O R M _ A I G E R _ G A T E S | ||
=======================================*/ | ||
int CompInfo::form_aiger_gates(DNF &Gates) | ||
{ | ||
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int ind = -1; | ||
assert(N->Outputs.size() == 1); | ||
size_t out_gate_ind = N->Outputs[0]; | ||
for (size_t i=0; i < N->Gate_list.size(); i++) { | ||
Gate &G = N->Gate_list[i]; | ||
if (G.gate_type == INPUT) continue; | ||
if (G.gate_type == LATCH) continue; | ||
if (G.func_type == CONST) continue; | ||
assert(G.ninputs <= 2); | ||
if (i == out_gate_ind) | ||
ind = Gates.size(); | ||
if (G.func_type == AND) { | ||
add_aiger_and_gate(Gates,i); | ||
continue; | ||
} | ||
assert(G.func_type == BUFFER); | ||
add_aiger_buffer(Gates,i); | ||
} | ||
assert(ind >= 0); | ||
return(ind); | ||
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} /* end of function form_aiger_gates */ | ||
/*================================= | ||
F I N D _ A I G E R _ L I T 1 | ||
================================*/ | ||
int CompInfo::find_aiger_lit1(int gate_ind,char polarity) | ||
{ | ||
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Gate &G = N->get_gate(gate_ind); | ||
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if (G.func_type == CONST) { | ||
if (G.F.size() > 0) return(1); | ||
else { | ||
assert(F.size() == 0); | ||
return(0); | ||
} | ||
} | ||
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int lit = (gate_ind+1) << 1; | ||
if (polarity) return(lit+1); | ||
else return(lit); | ||
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} /* end of function find_aiger_lit1 */ | ||
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/*================================= | ||
F I N D _ A I G E R _ L I T 2 | ||
================================*/ | ||
int CompInfo::find_aiger_lit2(int gate_ind,char polarity) | ||
{ | ||
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int lit = (gate_ind+1) << 1; | ||
if (polarity) return(lit+1); | ||
else return(lit); | ||
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} /* end of function find_aiger_lit2 */ | ||
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/*======================================== | ||
P R I N T _ A I G E R _ L A T C H E S | ||
======================================*/ | ||
void CompInfo::print_aiger_latches(FILE *fp) | ||
{ | ||
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for (size_t i=0; i < N->Latches.size(); i++) { | ||
int gate_ind = N->Latches[i]; | ||
int lit = (gate_ind+1) << 1; | ||
fprintf(fp,"%d ",lit); | ||
Gate &G = N->get_gate(gate_ind); | ||
assert(G.Fanin_list.size() == 1); | ||
int next_lit = find_aiger_lit1(G.Fanin_list[0],0); | ||
fprintf(fp,"%d ",next_lit); | ||
if (G.init_value == 2) { | ||
fprintf(fp,"%d\n",lit); | ||
continue;} | ||
assert((G.init_value == 0) || (G.init_value == 1)); | ||
fprintf(fp,"%d\n",G.init_value); | ||
} | ||
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} /* end of function print_aiger_latches */ | ||
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/*======================================== | ||
P R I N T _ A I G E R _ I N P S | ||
======================================*/ | ||
void CompInfo::print_aiger_inps(FILE *fp) | ||
{ | ||
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for (size_t i=0; i < N->Inputs.size(); i++) { | ||
int gate_ind = N->Inputs[i]; | ||
fprintf(fp,"%d\n",(gate_ind+1)<<1); | ||
} | ||
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} /* end of function print_aiger_inps */ | ||
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/*======================================== | ||
P R I N T _ A I G E R _ H E A D E R | ||
======================================*/ | ||
void CompInfo::print_aiger_header(FILE *fp,int max_var,int num_gates) | ||
{ | ||
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fprintf(fp,"aag "); | ||
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fprintf(fp,"%d ",max_var); | ||
fprintf(fp,"%d ",N->ninputs); | ||
fprintf(fp,"%d ",N->nlatches); | ||
fprintf(fp,"1 "); | ||
fprintf(fp,"%d",num_gates); | ||
if (Constr_gates.size() == 0) fprintf(fp,"\n"); | ||
else fprintf(fp," 0 %d\n",(int) Constr_gates.size()); | ||
} /* end of function print_aiger_header*/ | ||
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/*============================== | ||
C H E C K _ C I R C U I T | ||
===============================*/ | ||
void CompInfo::check_circuit(int &num_buffs,int &num_consts) | ||
{ | ||
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num_consts = 0; | ||
num_buffs = 0; | ||
for (size_t i=0; i < N->Gate_list.size(); i++) { | ||
Gate &G = N->Gate_list[i]; | ||
if (G.gate_type == INPUT) continue; | ||
if (G.gate_type == LATCH) continue; | ||
assert(G.gate_type == GATE); | ||
bool cond = (G.func_type == AND); | ||
cond |= (G.func_type == BUFFER); | ||
cond |= (G.func_type == CONST); | ||
if (!cond) { | ||
p(); | ||
print_func_type(G); | ||
exit(100); | ||
} | ||
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if (G.func_type == CONST) num_consts++; | ||
if (G.func_type == BUFFER) num_buffs++; | ||
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if (G.ninputs != 2) { | ||
bool cond = (i == N->Gate_list.size()-2); | ||
cond |= (G.func_type == BUFFER); | ||
cond |= (G.func_type == CONST); | ||
if (!cond) { | ||
p(); | ||
printf("i = %d\n",i); | ||
printf("N->Gate_list.size() = %d\n",(int) N->Gate_list.size()); | ||
printf("G.ninputs = %d\n",G.ninputs); | ||
exit(100); | ||
} | ||
} | ||
} | ||
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} /* end of function check_circuit */ |
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