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Bump CBMC dependency
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kroening committed Dec 18, 2024
1 parent 268e27e commit 090d419
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Showing 32 changed files with 33 additions and 38 deletions.
2 changes: 1 addition & 1 deletion regression/ebmc/range_type/range_type1.desc
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CORE broken-smt-backend
CORE
range_type1.smv
--bound 10
^EXIT=0$
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2 changes: 1 addition & 1 deletion regression/ebmc/range_type/range_type4.desc
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
range_type4.smv
--bound 10
^EXIT=0$
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2 changes: 1 addition & 1 deletion regression/ebmc/traces/disjunction1.desc
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
disjunction1.smv
--bound 20 --numbered-trace
^\[spec1\] G \(X FALSE \| X X FALSE\): REFUTED$
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2 changes: 1 addition & 1 deletion regression/smv/CTL/smv_ctlspec_F1.desc
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CORE broken-smt-backend
CORE
smv_ctlspec_F1.smv
--bound 10
^\[.*\] AF x = 0: REFUTED$
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2 changes: 1 addition & 1 deletion regression/smv/CTL/smv_ctlspec_G1.desc
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
smv_ctlspec_G1.smv
--bound 10
^\[.*\] AG x != 5: PROVED up to bound 10$
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2 changes: 1 addition & 1 deletion regression/smv/LTL/smv_ltlspec6.desc
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CORE broken-smt-backend
CORE
smv_ltlspec6.smv

^EXIT=0$
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2 changes: 1 addition & 1 deletion regression/smv/LTL/smv_ltlspec_F1.desc
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CORE broken-smt-backend
CORE
smv_ltlspec_F1.smv
--bound 10
^EXIT=10$
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2 changes: 1 addition & 1 deletion regression/smv/LTL/smv_ltlspec_F2.desc
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CORE broken-smt-backend
CORE
smv_ltlspec_F2.smv
--bound 10
^EXIT=10$
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2 changes: 1 addition & 1 deletion regression/smv/LTL/smv_ltlspec_F3.desc
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CORE broken-smt-backend
CORE
smv_ltlspec_F3.smv
--bound 10 --numbered-trace
^\[.*\] F x = 0: REFUTED$
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2 changes: 1 addition & 1 deletion regression/smv/LTL/smv_ltlspec_G1.desc
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CORE broken-smt-backend
CORE
smv_ltlspec_G1.smv
--bound 10
^EXIT=10$
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2 changes: 1 addition & 1 deletion regression/smv/LTL/smv_ltlspec_G2.desc
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CORE broken-smt-backend
CORE
smv_ltlspec_G2.smv
--bound 10
^EXIT=10$
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2 changes: 1 addition & 1 deletion regression/smv/LTL/smv_ltlspec_G3.desc
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CORE broken-smt-backend
CORE
smv_ltlspec_G3.smv
--bound 10 --numbered-trace
^\[.*\] G X x != 3: REFUTED$
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2 changes: 1 addition & 1 deletion regression/smv/LTL/smv_ltlspec_R1.desc
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
smv_ltlspec_R1.smv
--bound 10
^\[.*\] x >= 1 R x = 1: PROVED up to bound 10$
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2 changes: 1 addition & 1 deletion regression/smv/LTL/smv_ltlspec_R3.desc
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
smv_ltlspec_R3.smv
--bound 1
^\[.*\] FALSE R x != 3: PROVED up to bound 1$
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2 changes: 1 addition & 1 deletion regression/smv/LTL/smv_ltlspec_R4.desc
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CORE broken-smt-backend
CORE
smv_ltlspec_R4.smv
--bound 10
^\[.*\] FALSE R x != 0: PROVED up to bound 10$
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2 changes: 1 addition & 1 deletion regression/smv/LTL/smv_ltlspec_U1.desc
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
smv_ltlspec_U1.smv
--bound 3
\[.*\] TRUE U x = 3: PROVED up to bound 3$
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2 changes: 1 addition & 1 deletion regression/smv/LTL/smv_ltlspec_U2.desc
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
smv_ltlspec_U2.smv
--bound 10 --numbered-trace
^\[.*\] TRUE U x = 0: REFUTED$
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2 changes: 1 addition & 1 deletion regression/smv/expressions/smv_if1.desc
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
smv_if1.smv

^EXIT=0$
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
assignment-to-concatenation1.v
--bound 1
^EXIT=0$
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2 changes: 1 addition & 1 deletion regression/verilog/assignments/assignment-to-index1.desc
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
assignment-to-index1.v
--bound 1
^EXIT=0$
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2 changes: 1 addition & 1 deletion regression/verilog/generate/generate-for2.desc
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
generate-for2.v
--bound 0
^EXIT=0$
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2 changes: 1 addition & 1 deletion regression/verilog/generate/generate-reg1.desc
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
generate-reg1.v
--module main --bound 0
^EXIT=0$
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2 changes: 1 addition & 1 deletion regression/verilog/generate1/test.desc
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
main.v
--module main --bound 1
^EXIT=0$
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2 changes: 1 addition & 1 deletion regression/verilog/multiple_assign1/test.desc
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
main.v
--module main --bound 1
^EXIT=0$
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2 changes: 1 addition & 1 deletion regression/verilog/part-select/indexed-part-select1.desc
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
indexed-part-select1.sv
--bound 0
^EXIT=0$
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2 changes: 1 addition & 1 deletion regression/verilog/primitive_gates/nand1.desc
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
nand1.sv
--bound 0
^EXIT=0$
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2 changes: 1 addition & 1 deletion regression/verilog/primitive_gates/xnor3.desc
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
xnor3.sv
--bound 0
^\[main\.xnor_ok\] always main\.xnor_in1 ~\^ main\.xnor_in2 == main\.xnor_out: PROVED up to bound 0$
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2 changes: 1 addition & 1 deletion regression/verilog/system-functions/low1.desc
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@@ -1,4 +1,4 @@
CORE broken-smt-backend
CORE
low1.sv
--module main --bound 0
^EXIT=0$
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6 changes: 2 additions & 4 deletions src/ebmc/ebmc_parse_options.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -275,8 +275,7 @@ int ebmc_parse_optionst::doit()
netlistt netlist;
if(ebmc_base.make_netlist(netlist))
return 1;
auto filename =
cmdline.isset("outfile") ? cmdline.get_value("outfile") : "-";
auto filename = cmdline.value_opt("outfile").value_or("-");
output_filet outfile{filename};
outfile.stream() << "digraph netlist {\n";
netlist.output_dot(outfile.stream());
Expand All @@ -289,8 +288,7 @@ int ebmc_parse_optionst::doit()
netlistt netlist;
if(ebmc_base.make_netlist(netlist))
return 1;
auto filename =
cmdline.isset("outfile") ? cmdline.get_value("outfile") : "-";
auto filename = cmdline.value_opt("outfile").value_or("-");
output_filet outfile{filename};
outfile.stream() << "-- Generated by EBMC " << EBMC_VERSION << '\n';
outfile.stream() << "-- Generated from "
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1 change: 0 additions & 1 deletion src/hw_cbmc_irep_ids.h
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Expand Up @@ -238,7 +238,6 @@ IREP_ID_ONE(verilog_time)
IREP_ID_ONE(verilog_iff)
IREP_ID_ONE(verilog_implies)
IREP_ID_ONE(offset)
IREP_ID_ONE(xnor)
IREP_ID_ONE(specify)
IREP_ID_ONE(x)
IREP_ID_ONE(verilog_empty_item)
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6 changes: 2 additions & 4 deletions src/verilog/verilog_synthesis.cpp
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Expand Up @@ -1572,11 +1572,9 @@ void verilog_synthesist::synth_module_instance_builtin(
exprt op;

if(instance.type().id() == ID_bool)
op = not_exprt{
multi_ary_exprt{ID_xor, std::move(operands), instance.type()}};
op = not_exprt{xor_exprt{std::move(operands)}};
else
op = bitnot_exprt{
multi_ary_exprt{ID_bitxor, std::move(operands), instance.type()}};
op = bitnot_exprt{bitxor_exprt{std::move(operands), instance.type()}};

equal_exprt constraint{output, std::move(op)};
trans.invar().add_to_operands(std::move(constraint));
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