Verilog: grammar for binary ^~ xnor

diffblue · Nov 16, 2024 · 01eca40 · 01eca40
1 parent 6360d22
commit 01eca40
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/src/verilog/parser.y b/src/verilog/parser.y
@@ -3848,6 +3848,8 @@ expression:
 		{ init($$, ID_bitxor); mto($$, $1); mto($$, $3); }
 	| expression TOK_TILDECARET expression
 		{ init($$, ID_bitxnor); mto($$, $1); mto($$, $3); }
+	| expression TOK_CARETTILDE expression
+		{ init($$, ID_bitxnor); mto($$, $1); mto($$, $3); }
 	| expression TOK_LESSLESS expression
 		{ init($$, ID_shl); mto($$, $1); mto($$, $3); }
 	| expression TOK_LESSLESSLESS expression