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Verilog: grammar for unique case and unique if #658

Verilog: grammar for unique case and unique if

Verilog: grammar for unique case and unique if #658

Triggered via pull request April 22, 2024 15:56
@kroeningkroening
synchronize #446
unique_case1
Status Success
Total duration 1m 3s
Artifacts

syntax-checks.yaml

on: pull_request
check-clang-format
55s
check-clang-format
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