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Verilog: allow task invocations without parentheses #3311

Verilog: allow task invocations without parentheses

Verilog: allow task invocations without parentheses #3311

examples

succeeded Jan 28, 2025 in 5s
Set up job
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Run actions/checkout@v4
1s
Get the ebmc binary
1s
Try the ebmc binary
0s
ebmc on Hazard3
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Get the vlindex binary
0s
Try the vlindex binary
0s
vlindex on Hazard3
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Post Run actions/checkout@v4
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Complete job
0s