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Verilog: allow task invocations without parentheses #1995

Verilog: allow task invocations without parentheses

Verilog: allow task invocations without parentheses #1995

check-clang-format

succeeded Jan 28, 2025 in 1m 15s
Set up job
0s
Run actions/checkout@v4
1m 0s
Fetch dependencies
13s
Check updated lines of code match clang-format-15 style
0s
Post Run actions/checkout@v4
0s
Complete job
0s