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Add RISC-V Support #26

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1 change: 1 addition & 0 deletions common/cpucheck.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -204,6 +204,7 @@ int GetNumberOfDetectedProcessors( void )
#if (CLIENT_CPU == CPU_X86 || \
CLIENT_CPU == CPU_AMD64 || \
CLIENT_CPU == CPU_POWERPC || \
CLIENT_CPU == CPU_RISCV || \
CLIENT_CPU == CPU_S390 || \
CLIENT_CPU == CPU_S390X || \
CLIENT_CPU == CPU_PA_RISC)
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8 changes: 6 additions & 2 deletions common/cputypes.h
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Expand Up @@ -42,6 +42,7 @@
#define CPU_OPENCL 21
#define CPU_ARM64 22
#define CPU_PPC64 23
#define CPU_RISCV 24

/* DO NOT RECYCLE OLD OS SLOTS !!! (including OS_UNUSED_*) */
/* Old OSes will stay in stats forever! */
Expand Down Expand Up @@ -200,10 +201,12 @@
#define CLIENT_CPU CPU_IA64
#elif defined(__arm64__) || defined(__aarch64__)
#define CLIENT_CPU CPU_ARM64
#elif defined(__ppc64__) || defined(__PPC64__)
#elif defined(__ppc64__) || defined(__PPC64__)
#define CLIENT_CPU CPU_PPC64
#elif defined(ARM) || defined(__arm__)
#elif defined(ARM) || defined(__arm__)
#define CLIENT_CPU CPU_ARM
#elif defined(__riscv)
#define CLIENT_CPU CPU_RISCV
#elif defined(ASM_SPARC) || defined(__sparc__)
#define CLIENT_CPU CPU_SPARC
#elif defined(__PPU__) || defined(__SPU__)
Expand Down Expand Up @@ -615,6 +618,7 @@
(CLIENT_CPU == CPU_POWER) || (CLIENT_CPU == CPU_POWERPC) || \
(CLIENT_CPU == CPU_MIPS) || (CLIENT_CPU == CPU_ARM) || \
(CLIENT_CPU == CPU_AMD64) || (CLIENT_CPU == CPU_CUDA) || \
(CLIENT_CPU == CPU_RISCV) || \
(CLIENT_CPU == CPU_ATI_STREAM) || (CLIENT_CPU == CPU_OPENCL) || \
((CLIENT_CPU == CPU_ALPHA) && ((CLIENT_OS == OS_WIN32) || \
(CLIENT_OS == OS_DEC_UNIX))))
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25 changes: 23 additions & 2 deletions configure
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Expand Up @@ -527,6 +527,17 @@ add_sources() # $1=os, $2=arch, $3=custom
TARGET_ADDSRCS="$TARGET_ADDSRCS $OGRNG_GENERAL_SRCS $OGR/ansi/ogrng-32.cpp"
fi
#-----------------------------------------------------------------
elif [ "$2" = "riscv" ]; then
if [ "$HAVE_RC5_72" = "1"]; then
DEFAULT_RC5_72="1"
fi # HAVE_RC5_72

if [ "$HAVE_OGR" = "1" ]; then
DEFAULT_OGRNG="0"
#TARGET_ADDSRCS="$TARGET_ADDSRCS $OGRNG_GENERAL_SRCS $OGR/ppc/ogrng-ppc.cpp"
TARGET_ADDSRCS="$TARGET_ADDSRCS $OGRNG_GENERAL_SRCS $OGR/ansi/ogrng-32.cpp"
fi
#-----------------------------------------------------------------
elif [ "$2" = "arm64" ]; then
if [ "$HAVE_RC5_72" = "1" ]; then
DEFAULT_RC5_72="1"
Expand Down Expand Up @@ -966,7 +977,7 @@ gcc_get_ver() {
#gcc_v="gcc version 3.3 20030304 (Apple Computer, Inc. build 1495)"
#gcc_v="gcc version 4.0.1 (Apple Computer, Inc. build 5247)"
#gcc_v="gcc-Version 4.3.2 (Ubuntu 4.3.2-1ubuntu11)"

gccver_line=`echo $gcc_v|tail -1|tr '-' ' '`
#echo "gccver_line=#$gccver_line#"
lastwas=""
Expand Down Expand Up @@ -1676,7 +1687,7 @@ case "$1" in
add_sources "linux" "arm64"
;;

*linux-ppc64) # [sunset mikereed]
*linux-ppc64) # [sunset mikereed]
TARGET_CC="g++"
TARGET_AS="gcc -c"
TARGET_CCFLAGS="$OPTS_GCC -Wall -DHAVE_POSIX_THREADS"
Expand All @@ -1686,6 +1697,16 @@ case "$1" in
add_sources "linux" "ppc64"
;;

*linux-riscv) # [jka]
TARGET_CC="g++"
TARGET_AS="gcc -c"
TARGET_CCFLAGS="$OPTS_GCC -Wall -DHAVE_POSIX_THREADS"
TARGET_LIBS="-lpthread -lrt"
TARGET_TARBALL="linux-riscv"
TARGET_DOCFILES="docs/readme._ix"
add_sources "linux" "riscv"
;;

*linux-arm-elf_single) # [teichp]
TARGET_CC="gcc"
TARGET_AS="gcc -c"
Expand Down