init branch develop

.github/workflows/ci.yml

@@ -0,0 +1,24 @@
+name: CI
+on:
+  pull_request:
+    branches: [master]
+  push:
+    branches: [master]
+  # CI runs every 12 hours
+  schedule: [cron: "0 */12 * * *"]
+
+jobs:
+  ci-check:
+    name: CI Build and Simulate
+    runs-on: ubuntu-latest
+    strategy:
+      fail-fast: false
+    steps:
+      - uses: actions/checkout@v2
+      - name: build and simulate
+        run : |
+          ./setup.sh
+          ./run.sh
+      - name: Setup tmate session
+        if: ${{ failure() }}
+        uses: mxschmitt/action-tmate@v3

.gitignore

@@ -0,0 +1,4 @@
+**/build/**
+**/verilog/**
+**/*.log
+img/*.drawio

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "lib/blue_wrapper"]
+	path = lib/blue_wrapper
+	url = https://github.com/wengwz/blue-wrapper.git

Makefile.base

@@ -0,0 +1,26 @@
+TRANSFLAGS = -aggressive-conditions -lift # -split-if
+RECOMPILEFLAGS = -u -show-compiles
+SCHEDFLAGS = -show-schedule -sched-dot # -show-rule-rel dMemInit_request_put doExecute
+#	-show-elab-progress
+DEBUGFLAGS = -check-assert \
+	-continue-after-errors \
+	-keep-fires \
+	-keep-inlined-boundaries \
+	-show-method-bvi \
+	-show-method-conf \
+	-show-module-use \
+	-show-range-conflict \
+	-show-stats \
+	-warn-action-shadowing \
+	-warn-method-urgency \
+	-promote-warnings ALL
+VERILOGFLAGS = -verilog -remove-dollar -remove-unused-modules # -use-dpi -verilog-filter cmd
+BLUESIMFLAGS = -parallel-sim-link 16 # -systemc
+BUILDDIR = build
+OUTDIR = -bdir $(BUILDDIR) -info-dir $(BUILDDIR) -simdir $(BUILDDIR) -vdir $(BUILDDIR)
+WORKDIR = -fdir $(abspath .)
+LIBSRCDIR = $(abspath ../lib/blue_wrapper/src)
+BSVSRCDIR = -p +:$(abspath ../src):$(LIBSRCDIR)
+DIRFLAGS = $(BSVSRCDIR) $(OUTDIR) $(WORKDIR)
+MISCFLAGS = -print-flags -show-timestamps -show-version -steps 6000000 # -D macro
+RUNTIMEFLAGS = +RTS -K4095M -RTS

Makefile.test

@@ -0,0 +1,21 @@
+TESTDIR ?= $(abspath ../test)
+LOGDIR ?= $(abspath ../tmp)
+
+TESTBENCHS = \
+			TestStreamUtils.bsv \
+            TestDmaCore.bsv
+
+TestStreamUtils.bsv					= mkStreamConcatTb \
+								 	    mkStreamSplitTb
+TestDmaCore.bsv                  	= mkChunkComputerTb 
+
+all: $(TESTBENCHS)
+
+%.bsv:
+	$(foreach testcase, $($@), $(shell cd $(TESTDIR) && make simulate TESTFILE=$@ TOPMODULE=$(testcase) > $(LOGDIR)/$@-$(testcase).log 2>&1))
+
+clean:
+	rm -f $(LOGDIR)/*.log
+
+.PHONY: all TESTBENCHS %.bsv clean
+.DEFAULT_GOAL := all

backend/Makefile

@@ -0,0 +1,40 @@
+include ../Makefile.base
+
+TCLDIR ?= xdc
+CLK ?= rdma_clock
+OOC ?= 1
+VLOGDIR ?= verilog
+OUTPUTDIR ?= output
+LOGFILE ?= run.log
+RUNTOPHASE ?= place # synth place route all
+PARTNAME = xcvu13p-fhgb2104-2-i
+TARGETFILE ?= ../src/DmaWrapper.bsv
+TOPMODULE ?= mkRawSimpleDmaController
+
+export TOP = $(TOPMODULE)
+export RTL = $(VLOGDIR)
+export XDC = $(TCLDIR)
+export IPS = $(SRCDIR)/ip/$(PARTNAME)
+export CLOCKS = $(CLK)
+export OUTPUT = $(OUTPUTDIR)
+export OOCSYNTH = $(OOC)
+export RUNTO = $(RUNTOPHASE)
+export PART = $(PARTNAME)
+
+compile:
+	mkdir -p $(BUILDDIR)
+	bsc -elab -sim -verbose $(BLUESIMFLAGS) $(DEBUGFLAGS) $(DIRFLAGS) $(MISCFLAGS) $(RECOMPILEFLAGS) $(RUNTIMEFLAGS) $(SCHEDFLAGS) $(TRANSFLAGS) -g $(TOPMODULE) $(TARGETFILE)
+
+verilog: compile
+	mkdir -p $(VLOGDIR)
+	bsc $(VERILOGFLAGS) $(DIRFLAGS) $(MISCFLAGS) $(RECOMPILEFLAGS) $(RUNTIMEFLAGS) $(TRANSFLAGS) -g $(TOPMODULE) $(TARGETFILE)
+	bluetcl listVlogFiles.tcl -bdir $(BUILDDIR) -vdir $(BUILDDIR) $(TOPMODULE) $(TOPMODULE) | grep -i '\.v' | xargs -I {} cp {} $(VLOGDIR)
+
+# vivado: verilog
+# 	vivado -mode tcl -nolog -nojournal -source ./non_project_build.tcl 2>&1 | tee $(LOGFILE)
+
+clean:
+	rm -rf $(BUILDDIR) $(OUTPUTDIR) $(VLOGDIR) .Xil *.jou *.log
+
+.PHONY: verilog vivado clean
+.DEFAULT_GOAL := verilog

backend/listVlogFiles.tcl

@@ -0,0 +1,223 @@
+#!/bin/sh
+
+# \
+exec $BLUESPECDIR/bin/bluetcl "$0" "$@"
+
+package require utils
+
+proc usage {} {
+    puts ""
+    puts "usage: $::argv0 <options> top_package_name top_module"
+    puts "Options:"
+    puts "  -q             Do not print section headers"
+    puts "  -p <path>      Bluespec search path"
+    puts "  -bdir <dir>    Bluespec bdir directory"
+    puts "  -vdir <dir>    Bluespec vdir directory"
+    puts "  -generated     Print synthesized BSV modules"
+    puts "  -primitives    Print Bluespec primitive modules"
+    puts "  -imported      Print imported modules"
+    puts "  -no-inline-fns Print modules for no-inline functions"
+    puts "  -all           Alias for -generated -primitives -imported -no-inline-fns"
+    puts ""
+    puts " e.g: -bdir build -p build:+ -vdir rtl mkTop fpga_a"
+}
+
+set boolOptions [list -- -q -generated -primitives -imported -no-inline-fns -all]
+set valOptions [list -p -bdir -vdir]
+
+if { [catch [list ::utils::scanOptions $boolOptions $valOptions true OPT "$argv"] opts] } {
+    puts stderr $opts
+    usage
+    exit 1
+}
+
+if {[llength $opts] == 0} {
+    puts stderr "A package name argument is required"
+    usage
+    exit 1
+}
+
+if {[llength $opts] == 1} {
+    puts stderr "A top module name is required"
+    usage
+    exit 1
+}
+
+if {[llength $opts] > 2} {
+    puts stderr "Too many arguments"
+    usage
+    exit 1
+}
+
+if { [info exists OPT(-p)] } {
+    Bluetcl::flags set -p $OPT(-p)
+}
+if { [info exists OPT(-bdir)] } {
+    Bluetcl::flags set -bdir $OPT(-bdir)
+}
+if { [info exists OPT(-vdir)] } {
+    Bluetcl::flags set -vdir $OPT(-vdir)
+}
+
+if {![info exists OPT(-all)] && ![info exists OPT(-generated)] &&
+    ![info exists OPT(-no-inline-fns)] && ![info exists OPT(-primitives)] &&
+    ![info exists OPT(-imported)]} {
+    set OPT(-all) 1
+}
+
+set top_pkg [lindex $opts 0]
+set top_mod [lindex $opts 1]
+
+# Assume -verilog
+Bluetcl::flags set -verilog
+
+# Load the module information
+Bluetcl::module load $top_pkg
+
+# Walk the hierarchy extracting module information
+set mods_to_process [list $top_pkg]
+set already_done [list]
+set is_noinline 0
+while {[llength $mods_to_process] > 0} {
+    set this_mod [utils::head $mods_to_process]
+    set mods_to_process [utils::tail $mods_to_process]
+    set res [Bluetcl::module submods $this_mod]
+    set this_mod_type [lindex $res 0]
+    if {$this_mod_type == "user" && $is_noinline != 0} {
+	set this_mod_type "no-inline-fn"
+    }
+    array set mod_info [list $this_mod $this_mod_type]
+    lappend already_done $this_mod
+    set sub_mods [lindex $res 1]
+    set no_inlines [lindex $res 2]
+    foreach mod $sub_mods {
+        set this_sub_mod [utils::snd $mod]
+	if {[lsearch -exact $already_done $this_sub_mod] == -1 &&
+	    [lsearch -exact $mods_to_process $this_sub_mod] == -1 } {
+	    lappend mods_to_process $this_sub_mod
+	}
+    }
+    set is_noinline 1
+    foreach mod $no_inlines {
+        set this_sub_mod [utils::snd $mod]
+	if {[lsearch -exact $already_done $this_sub_mod] == -1 &&
+	    [lsearch -exact $mods_to_process $this_sub_mod] == -1 } {
+	    lappend mods_to_process $this_sub_mod
+	}
+    }
+    set is_noinline 0
+}
+
+# Procedure to locate a file for a given module
+proc lookupfile {name path exts} {
+    foreach dir $path {
+	foreach ext $exts {
+	    set fname [join [list $name $ext] "."]
+	    set fpath [file join $dir $fname]
+	    if {[file exist $fpath]} {
+	        return [file normalize $fpath]
+	    }
+	}
+    }
+    return "<unable to locate file for module $name>"
+}
+
+# Procedure to add a file to a list, avoiding duplication
+proc addfile {name flName} {
+    upvar 1 $flName file_list
+
+    set matched 0
+    foreach f $file_list {
+	if {$f == $name} {
+	   set matched 1
+	   break
+        }
+    }
+    if {$matched == 0} {
+       lappend file_list $name
+    }
+}
+
+# Identify the location of each module's file
+set user_mods    [list]
+set noinline_fns [list]
+set primitives   [list]
+set imported     [list]
+
+set vdir [lindex [Bluetcl::flags show vdir] 1]
+set bsdir $::env(BLUESPECDIR)
+
+set libs [list [file join $bsdir "Verilog"] [file join $bsdir "Libraries"]]
+set vsearch [split [lindex [Bluetcl::flags show p] 1] ":"]
+set vdir_and_libs [concat $vdir $libs]
+set vsearch_and_libs [concat $vsearch $libs]
+
+foreach mod [array names mod_info] {
+    set mod_type $mod_info($mod)
+
+    # The Probe primitive has no associated Verilog module
+    if {$mod_type == "primitive" && $mod == "Probe"} {
+        continue
+    }
+
+    # Add the module info to the correct list
+    switch -exact $mod_type {
+	"user"         {addfile [lookupfile $mod $vdir_and_libs {v}] user_mods}
+        "no-inline-fn" {addfile [lookupfile $mod $vdir {v}] noinline_fns}
+        "primitive"    {addfile [lookupfile $mod $libs {v}] primitives}
+        "import"       {addfile [lookupfile $mod $vsearch_and_libs {v vhd vhdl}] imported}
+    }
+
+    # Some primitives use other primitives
+    if {$mod_type == "primitive"} {
+	switch -exact $mod {
+	    "MakeReset"     {addfile [lookupfile "SyncReset" $libs {v}] primitives}
+	    "MakeResetA"    {addfile [lookupfile "SyncResetA" $libs {v}] primitives}
+	    "SyncFIFOLevel" {addfile [lookupfile "ClockGen" $libs {v}] primitives
+		             addfile [lookupfile "SyncHandshake" $libs {v}] primitives
+                            }
+	    "SyncFIFO"      {addfile [lookupfile "ClockGen" $libs {v}] primitives}
+	    "SyncRegister " {addfile [lookupfile "ClockGen" $libs {v}] primitives
+		             addfile [lookupfile "SyncHandshake" $libs {v}] primitives
+                            }
+        }
+    }
+}
+
+if {[llength $user_mods] > 0 && ([info exists OPT(-generated)] || [info exists OPT(-all)])} {
+    if {![info exists OPT(-q)]} {
+        puts "# Synthesized user modules:"
+    }
+    foreach file $user_mods {
+	puts $file
+    }
+}
+
+if {[llength $noinline_fns] > 0 && ([info exists OPT(-no-inline-fns)] || [info exists OPT(-all)])} {
+    if {![info exists OPT(-q)]} {
+        puts "# No-inlined functions:"
+    }
+    foreach file $noinline_fns {
+	puts $file
+    }
+}
+
+if {[llength $imported] > 0 && ([info exists OPT(-imported)] || [info exists OPT(-all)])} {
+    if {![info exists OPT(-q)]} {
+        puts "# Imported modules:"
+    }
+    foreach file $imported {
+	puts $file
+    }
+}
+
+if {[llength $primitives] > 0 && ([info exists OPT(-primitives)] || [info exists OPT(-all)])} {
+    if {![info exists OPT(-q)]} {
+        puts "# Bluespec library primitives:"
+    }
+    foreach file $primitives {
+	puts $file
+    }
+}
+
+exit

cocotb/Makefile

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+ROOT_DIR = $(abspath ../)
+BACKEND_DIR = $(ROOT_DIR)/backend
+TB_DIR = $(abspath ./)
+include $(ROOT_DIR)/Makefile.base
+VBUILD_DIR = $(BACKEND_DIR)/build 
+VSRC_DIR = $(BACKEND_DIR)/verilog
+
+TARGET = RawDmaController
+TOP_MODULE = mk$(TARGET)
+TOP_FILE = $(TOP_MODULE).v
+VLOG_FILE = $(TB_DIR)/$(TOP_FILE)
+
+TB_CASE = dma_fullypipeline
+TB_FILE = $(TB_CASE)_tb.py
+DATE = $(shell date "+%Y%m%d")
+LOG_FILE = $(TB_DIR)/log/$(DATE)_$(TOP_MODULE).log
+
+verilog:
+	cd $(BACKEND_DIR) && make verilog
+
+prepare:
+	rm -rf $(VLOG_FILE)
+	bluetcl $(BACKEND_DIR)/listVlogFiles.tcl -bdir $(VBUILD_DIR) -vdir $(VSRC_DIR) $(TOP_MODULE) $(TOP_MODULE) | grep -i '\.v' | xargs -I {} cat {} >> $(VLOG_FILE)
+	sed -i '1i `timescale 1ns/1ps' $(VLOG_FILE)
+
+run:
+	cd $(TB_DIR)
+	mkdir -p log
+	python3 $(TB_FILE) 2>&1 | tee $(LOG_FILE)
+
+cocotb:clean verilog prepare run
+
+clean:
+	cd $(BACKEND_DIR) && make clean
+	cd $(TB_DIR) && rm -rf $(VLOG_FILE) __pycache__ .pytest_cache sim_build *.log 
+