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init branch develop #1

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f3d3de9
Initialize base types
BIGWJZ Jul 3, 2024
03eb410
init branch develop
BIGWJZ Jul 4, 2024
765d837
Inplement PCIe Interface Types
BIGWJZ Jul 4, 2024
f259b91
Inplement PCIe Interface Types
BIGWJZ Jul 4, 2024
a4a8d12
update mkChunkComputer
BIGWJZ Jul 5, 2024
2cc532c
Add mkChunkComputeTb and test pass
BIGWJZ Jul 7, 2024
89dfb11
Dynamic TLP Max Payload Size
BIGWJZ Jul 8, 2024
85baea7
Dynamic TLP Max Payload Size
BIGWJZ Jul 8, 2024
00a6386
Test various MPS settings and verify timing
BIGWJZ Jul 9, 2024
5e6b009
Add StreamUtils::StreamConcat
BIGWJZ Jul 10, 2024
75ebadb
a simple test:
BIGWJZ Jul 10, 2024
1b76335
a simple test
BIGWJZ Jul 10, 2024
ebc614f
Test Pass
BIGWJZ Jul 11, 2024
d20503f
Update StreamUtils
BIGWJZ Jul 11, 2024
9c0ac45
Add StreamSplit
BIGWJZ Jul 12, 2024
4f92212
Test StreamUtils Pass
BIGWJZ Jul 13, 2024
44e0f8a
Update all modules according to the review
BIGWJZ Jul 14, 2024
3267090
Update StreaUtils
BIGWJZ Jul 16, 2024
9fb805d
update PcieTypes
BIGWJZ Jul 16, 2024
0c9018d
Add CompleterRequest
BIGWJZ Jul 20, 2024
ddc177a
Fix Types
BIGWJZ Jul 20, 2024
c7d7d77
Add PcieCompleter
BIGWJZ Jul 20, 2024
b70f57d
Add CCDescriptor and modify interface
BIGWJZ Jul 21, 2024
31d1b0f
Update dmac interfaces
BIGWJZ Jul 21, 2024
cc29df5
testDmaCompterRequest
BIGWJZ Jul 21, 2024
27d3953
Add TestDmacVivado for simulation with IP
BIGWJZ Jul 23, 2024
438dda2
Update rawPcie interfaces
BIGWJZ Jul 23, 2024
ec3c3f4
Finish CsrWrRd
BIGWJZ Jul 25, 2024
98c2005
Fix streamUtils and pass all test
BIGWJZ Jul 25, 2024
ac1beec
Add dmaRequester
BIGWJZ Aug 2, 2024
63777bc
Add streamShift
BIGWJZ Aug 5, 2024
0636564
Add streamShift
BIGWJZ Aug 5, 2024
39de089
Add ReqRequestCore
BIGWJZ Aug 6, 2024
7cd136b
Reorganize DmaC2HPipe and PCIe adapter interfaces
BIGWJZ Aug 14, 2024
a84cd31
Reorganize DmaC2HPipe&DmaH2CPipe
BIGWJZ Aug 16, 2024
bc89604
Add RawDmaController Wrapper and a simple cocotb
BIGWJZ Aug 21, 2024
9426c06
Add cocotb testbench
BIGWJZ Aug 27, 2024
db450a5
Pass cocotb write tb
BIGWJZ Aug 30, 2024
1ad356c
Pass straddle mode cocotb test
BIGWJZ Sep 3, 2024
d1f9974
Add H2C functions
BIGWJZ Sep 21, 2024
7af1a43
Add Simple Mode
BIGWJZ Oct 8, 2024
f9e46fa
solve h2c r&w
BIGWJZ Oct 12, 2024
875df73
add cocotb bar tb
BIGWJZ Oct 15, 2024
d4d5a4c
pass simple mode tb
BIGWJZ Oct 16, 2024
15ef729
Add read-write loop tb
BIGWJZ Oct 16, 2024
10666a5
optimize for fully-pipeline
BIGWJZ Oct 28, 2024
35c503d
Add blue-rdma style interface
BIGWJZ Nov 7, 2024
cb50bdc
Add blue-rdma style interface
BIGWJZ Nov 7, 2024
e146e69
avoid same name file in blue-rdma
BIGWJZ Nov 7, 2024
cb2073c
Fix User Bar Problems
BIGWJZ Nov 29, 2024
30f7649
Fix C2HPipe.reshapeMRRS and cocotb.loop
BIGWJZ Dec 3, 2024
0c5ac0d
Fix TlpOutMux
BIGWJZ Dec 3, 2024
3e9e8f6
Add DummyCsr of Bypass Mode
BIGWJZ Dec 6, 2024
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3 changes: 3 additions & 0 deletions .gitmodules
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[submodule "lib/blue_wrapper"]
path = lib/blue_wrapper
url = https://github.com/wengwz/blue-wrapper.git
100 changes: 100 additions & 0 deletions img/split.drawio
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<mxfile host="65bd71144e">
<diagram id="kbZJOYVz6SfErWRKv-7J" name="第 1 页">
<mxGraphModel dx="979" dy="633" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="827" pageHeight="1169" math="0" shadow="0">
<root>
<mxCell id="0"/>
<mxCell id="1" parent="0"/>
<mxCell id="5" style="edgeStyle=none;html=1;exitX=1;exitY=0.5;exitDx=0;exitDy=0;entryX=0;entryY=0.5;entryDx=0;entryDy=0;" parent="1" source="2" target="4" edge="1">
<mxGeometry relative="1" as="geometry"/>
</mxCell>
<mxCell id="2" value="FifoIn" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
<mxGeometry x="40" y="150" width="80" height="40" as="geometry"/>
</mxCell>
<mxCell id="7" style="edgeStyle=none;html=1;exitX=1;exitY=0.5;exitDx=0;exitDy=0;entryX=0;entryY=0.5;entryDx=0;entryDy=0;" parent="1" source="4" target="6" edge="1">
<mxGeometry relative="1" as="geometry"/>
</mxCell>
<mxCell id="4" value="getFirstChunkLen" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
<mxGeometry x="170" y="140" width="120" height="60" as="geometry"/>
</mxCell>
<mxCell id="9" style="edgeStyle=none;html=1;exitX=1;exitY=0.5;exitDx=0;exitDy=0;entryX=0;entryY=0.5;entryDx=0;entryDy=0;" parent="1" source="6" target="8" edge="1">
<mxGeometry relative="1" as="geometry"/>
</mxCell>
<mxCell id="6" value="splitFifo" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
<mxGeometry x="340" y="150" width="57" height="40" as="geometry"/>
</mxCell>
<mxCell id="13" style="edgeStyle=none;html=1;exitX=0.5;exitY=1;exitDx=0;exitDy=0;entryX=0.5;entryY=0;entryDx=0;entryDy=0;" parent="1" source="8" target="12" edge="1">
<mxGeometry relative="1" as="geometry"/>
</mxCell>
<mxCell id="8" value="genSplitChunks" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
<mxGeometry x="440" y="140" width="120" height="60" as="geometry"/>
</mxCell>
<mxCell id="10" value="&lt;ul&gt;&lt;li&gt;dmaRequest&lt;/li&gt;&lt;ul&gt;&lt;li&gt;startAddr&lt;/li&gt;&lt;li&gt;length&lt;/li&gt;&lt;/ul&gt;&lt;li&gt;firstChunkLen&lt;/li&gt;&lt;/ul&gt;" style="rounded=1;whiteSpace=wrap;html=1;align=left;" parent="1" vertex="1">
<mxGeometry x="287" y="20" width="153" height="90" as="geometry"/>
</mxCell>
<mxCell id="12" value="FifoOut" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
<mxGeometry x="460" y="260" width="80" height="40" as="geometry"/>
</mxCell>
<mxCell id="15" value="" style="html=1;shadow=0;dashed=0;align=center;verticalAlign=middle;shape=mxgraph.arrows2.uTurnArrow;dy=3.58;arrowHead=29.5;dx2=25.14;rotation=90;" parent="1" vertex="1">
<mxGeometry x="490" y="80" width="50" height="60" as="geometry"/>
</mxCell>
<mxCell id="16" value="&lt;ul&gt;&lt;li&gt;startAddr&lt;/li&gt;&lt;li&gt;length&lt;/li&gt;&lt;/ul&gt;" style="rounded=1;whiteSpace=wrap;html=1;align=left;" parent="1" vertex="1">
<mxGeometry x="25" y="220" width="110" height="60" as="geometry"/>
</mxCell>
<mxCell id="18" value="&lt;ul&gt;&lt;li&gt;startAddr&lt;/li&gt;&lt;li&gt;length&lt;/li&gt;&lt;/ul&gt;" style="rounded=1;whiteSpace=wrap;html=1;align=left;" parent="1" vertex="1">
<mxGeometry x="445" y="310" width="110" height="60" as="geometry"/>
</mxCell>
<mxCell id="19" value="&lt;ul&gt;&lt;li&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;newChunkPtrReg&lt;/span&gt;&lt;/li&gt;&lt;li&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;totalLenRemainReg&lt;/span&gt;&lt;/li&gt;&lt;li&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;isSplittingReg&lt;/span&gt;&lt;/li&gt;&lt;/ul&gt;" style="rounded=1;whiteSpace=wrap;html=1;align=left;" parent="1" vertex="1">
<mxGeometry x="590" y="140" width="180" height="60" as="geometry"/>
</mxCell>
<mxCell id="20" value="4KB" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
<mxGeometry x="70" y="360" width="120" height="60" as="geometry"/>
</mxCell>
<mxCell id="21" value="4KB" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
<mxGeometry x="190" y="360" width="120" height="60" as="geometry"/>
</mxCell>
<mxCell id="22" value="4KB" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
<mxGeometry x="310" y="360" width="120" height="60" as="geometry"/>
</mxCell>
<mxCell id="26" value="offset" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
<mxGeometry x="150" y="400" width="40" height="60" as="geometry"/>
</mxCell>
<mxCell id="27" value="" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
<mxGeometry x="150" y="470" width="10" height="60" as="geometry"/>
</mxCell>
<mxCell id="28" value="512&lt;br&gt;√" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
<mxGeometry x="160" y="470" width="30" height="60" as="geometry"/>
</mxCell>
<mxCell id="29" value="512&lt;br&gt;√" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
<mxGeometry x="190" y="470" width="30" height="60" as="geometry"/>
</mxCell>
<mxCell id="30" value="512&lt;br&gt;√" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
<mxGeometry x="220" y="470" width="30" height="60" as="geometry"/>
</mxCell>
<mxCell id="31" value="firstChunk" style="text;html=1;strokeColor=none;fillColor=none;align=center;verticalAlign=middle;whiteSpace=wrap;rounded=0;" parent="1" vertex="1">
<mxGeometry x="100" y="530" width="60" height="30" as="geometry"/>
</mxCell>
<mxCell id="32" value="512&lt;br&gt;√" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
<mxGeometry x="150" y="300" width="30" height="60" as="geometry"/>
</mxCell>
<mxCell id="33" value="512&lt;br&gt;×" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
<mxGeometry x="180" y="300" width="30" height="60" as="geometry"/>
</mxCell>
<mxCell id="34" value="512&lt;br&gt;×" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
<mxGeometry x="210" y="300" width="30" height="60" as="geometry"/>
</mxCell>
<mxCell id="35" value="..." style="text;html=1;strokeColor=none;fillColor=none;align=center;verticalAlign=middle;whiteSpace=wrap;rounded=0;" parent="1" vertex="1">
<mxGeometry x="260" y="485" width="60" height="30" as="geometry"/>
</mxCell>
<mxCell id="36" value="..." style="text;html=1;strokeColor=none;fillColor=none;align=center;verticalAlign=middle;whiteSpace=wrap;rounded=0;" parent="1" vertex="1">
<mxGeometry x="240" y="315" width="60" height="30" as="geometry"/>
</mxCell>
<mxCell id="37" value="" style="endArrow=none;dashed=1;html=1;strokeColor=#CC0066;" edge="1" parent="1">
<mxGeometry width="50" height="50" relative="1" as="geometry">
<mxPoint x="190" y="550" as="sourcePoint"/>
<mxPoint x="190" y="260" as="targetPoint"/>
</mxGeometry>
</mxCell>
</root>
</mxGraphModel>
</diagram>
</mxfile>
1 change: 1 addition & 0 deletions lib/blue_wrapper
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Submodule blue_wrapper added at 0845f3
7 changes: 7 additions & 0 deletions src/DmaController.bsv
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import PcieTypes::*;
import DmaTypes::*;

module mkDmaController#() (DmaController ifc);


endmodule
99 changes: 99 additions & 0 deletions src/DmaRequestCore.bsv
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import FIFOF::*;
import PcieTypes::*;
import DmaTypes::*;

typedef 4096 BUS_BOUNDARY
typedef 12 BUS_BOUNDARY_WIDTH
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typedef struct {
DmaRequestFrame dmaRequest;
Maybe#(DmaMemAddr) firstChunkLen;
} ChunkRequestFrame deriving(Bits, Eq);

Interface ChunkCompute;
FifoIn#(DmaRequestFrame) dmaRequests;
FifoOut#(DmaRequestFrame) chunkRequests;
endinterface

module mkChunkComputer(ChunkCompute ifc);
FIFOF#(DmaRequestFrame) inputFifo <- mkFIFOF;
FIFOF#(DmaRequestFrame) outputFifo <- mkFIFOF;
FIFOF#(ChunkRequestFrame) splitFifo <- mkFIFOF;

Reg#(DmaMemAddr) newChunkPtrReg <- mkReg(0);
Reg#(DmaMemAddr) totalLenRemainReg <- mkReg(0);
Reg#(Bool) isSplittigReg <- mkReg(False);

function Bool hasBoundary(DmaRequestFrame request);
let highIdx = (request.startAddr + request.length) >> BUS_BOUNDARY_WIDTH;
let lowIdx = request.startAddr >> BUS_BOUNDARY_WIDTH;
return (highIdx > lowIdx);
endfunction

function DmaMemAddr getOffset(DmaRequestFrame request);
DmaMemAddr offset = zeroExtend(fromInteger(valueOf(BUS_BOUNDARY)) - pack(request.startAddr[BUS_BOUNDARY_WIDTH-1:0]));
return offset;
endfunction

rule getfirstChunkLen if(inputFifo.notEmpty && splitFifo.notFull);
let request = inputFifo.first;
inputFifo.deq;
let offset = getOffSet(request);
// firstChunkLen = offset % PCIE_TLP_BYTES
DmaMemAddr firstLen = zeroExtend(offset[valueOf(PCIE_TLP_BYTES_WIDTH)-1:0]);
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you have to read the PG213 to find out how to get the Max Payload Size(MPS) and Max Read Request Size(MRRS), those value is not const so you should do some refacrtor.

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MPS&MRRS are passed in the Configuration Status Interface Port . They should be parameters of my module.
image

image

ChunkRequestFrame splitRequest = {
dmaRequest: request,
firstChunkLen: hasBoundary(request) ? tagged Valid firstLen : tagged Invalid;
}
splitFifo.enq(splitRequest);
endrule

rule execSplit if(splitFifo.notEmpty && outFifo.notFull);
let splitRequest = splitFifo.first;
if (isSplittingReg) begin
if (totalLenRemainReg <= PCIE_TLP_BYTES) begin
isSplittingReg <= False;
outputFifo.enq(DmaRequestFrame {
startAddr: newChunkPtrReg;
length: totalLenRemainReg;
});
splitFifo.deq;
totalLenRemainReg <= 0;
end else begin
isSplittingReg <= True;
outputFifo.enq(DmaRequestFrame {
startAddr: newChunkPtrReg;
length: fromInteger(valueOf(PCIE_TLP_BYTES));
});
newChunkPtrReg <= newChunkPtrReg + fromInteger(valueOf(PCIE_TLP_BYTES));
totalLenRemainReg <= totalLenRemainReg - PCIE_TLP_BYTES;
end
end else begin
let remainderLength = splitRequest.dmaRequest.length - fromMaybe(0, splitRequest.firstChunkLen);
if (isValid(splitRequest.firstChunkLen)) begin
Bool isSplittingNextCycle = (remainderLength > 0);
isSplittingReg <= isSplittingNextCycle;
outputFifo.enq(DmaRequestFrame {
startAddr: splitRequest.dmaRequest.startAddr;
length: fromMaybe(0, splitRequest.firstChunkLen);
});
if (!isSplittingNextCycle) begin splitFifo.deq; end;
newChunkPtrReg <= splitRequest.dmaRequest + fromMaybe(0, splitRequest.firstChunkLen);
totalLenRemainReg <= remainderLength;
end else begin
Bool isSplittingNextCycle = (remainderLength > PCIE_TLP_BYTES);
isSplittingReg <= isSplittingNextCycle;
outputFifo.enq(DmaRequestFrame {
startAddr: splitRequest.dmaRequest.startAddr;
length: fromInteger(valueOf(PCIE_TLP_BYTES));
});
if (!isSplittingNextCycle) begin splitFifo.deq; end
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newChunkPtrReg <= newChunkPtrReg + fromInteger(valueOf(PCIE_TLP_BYTES));
totalLenRemainReg <= remainderLength - PCIE_TLP_BYTES;
end
end
endrule

interface dmaRequests = convertFifoToFifoOut(inputFifo);
interface chunkRequests = convertFifoToFifoOut(outputFifo);
endmodule
45 changes: 45 additions & 0 deletions src/DmaTypes.bsv
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import SemiFifo :: *;
import PcieTypes :: *;

typedef 512 DMA_DATA_WIDTH;
typedef 64 DMA_HOSTMEM_ADDR_WIDTH;
typedef 32 DMA_CSR_ADDR_WIDTH;
typedef 32 DMA_CSR_DATA_WIDTH;
typedef Bit#(DMA_HOSTMEM_ADDR_WIDTH) DmaMemAddr;
typedef Bit#(DMA_CSR_ADDR_WIDTH) DMACsrAddr;
typedef Bit#(DMA_CSR_DATA_WIDTH) DMACsrValue;

typedef struct {
Bit#(dataWidth) data;
Bit#(TDiv#(dataWidth, BYTE_BITS)) byteEn;
Bool isFirst;
Bool isLast;
} DataFrame#(numeric type dataWidth) deriving(Bits, Bounded, Eq, FShow);

typedef struct {
DmaMemAddr startAddr;
DmaMemAddr length;
} DmaRequestFrame deriving(Bits, Bounded, Eq, FShow);

typedef struct {
DMACsrAddr address;
DMACsrValue value;
} DmaCsrFrame deriving(Bits, Bounded, Eq, FShow);

interface DmaController#(numeric type dataWidth);

interface FifoIn#(DataFrame#(dataWidth)) DmaDataC2HPipeIn;
interface FifoIn#(DmaRequestFrame) DmaCtrlC2HPipeIn;
interface FifoIn#(DmaRequestFrame) DmaCtrlH2CPipeIn;
interface FifoOut#(DataFrame#(dataWidth)) DmaDataH2CPipeOut;

interface FifoIn#(DmaCsrFrame) DmaCsrC2HPipeIn;
interface FifoOut#(DMACsrAddr) DmaCsrC2HPipeOut;
interface FifoOut#(DmaCsrFrame) DmaCsrH2CPipeOut;

interface RawPcieRequester PcieRequester;
interface RawPcieCompleter PcieCompleter;
interface RawPcieConfiguration PcieConfig;

endinterface
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