Handle mapped form of neura.add in interpreter#322
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After --map-to-accelerator, compile-time constant operands are folded into rhs_value attributes, leaving a single SSA operand. The interpreter previously rejected any neura.add with fewer than two SSA operands. Extend handleAddOp to detect the single-operand mapped form and read the constant from the rhs_value IntegerAttr. The $rhs field in AddOp is already Optional<AnyType> (NeuraOps.td), so this is the intended post-mapping representation. Add a corresponding lit test using neura.grant_once + neura.add with rhs_value to verify 10 + 5 = 15. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
tancheng
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What are we actually targeting? I mean should we target a kernel like: https://github.com/coredac/neura/blob/main/test/e2e/fir/fir_kernel.mlir? and support all the missing ops required by that kernel?
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Good job. This issue definitely exists in similar ops as well. |
Thanks for chiming in @itemkelvin. @TimJZ Can you please share your slides with @itemkelvin so that you two can split the workloads? One can focus on CFG validation and the other one can focus on DFG validation. @ShangkunLi can you invite both of them into your discord space, so we can share stuff? You can create a neura-interpreter space/community/group. |
Hi~ @itemkelvin @TimJZ, here is the Discord space link https://discord.gg/UfaUCT3AyQ, plz feel free to discuss in it. |
Yeah sure! @itemkelvin Could you share an email address with me? I have some slides on Google Slides, and we can discuss offline on how to split the workload. Thanks! |
Background
The Neura spatial mapper (`--map-to-accelerator`) transforms pre-mapping IR into a tile-assigned, physically-routed form. As part of this transformation, compile-time constant operands are folded from SSA values into operation attributes. Specifically, an instruction like:
```mlir
%res = "neura.add"(%lhs, %const_1) : (!neura.data<i64, i1>, !neura.data<i64, i1>) -> !neura.data<i64, i1>
```
becomes:
```mlir
%res = "neura.add"(%lhs) {rhs_value = 1 : i64} : (!neura.data<i64, i1>) -> !neura.data<i64, i1>
```
This single-SSA-operand form is the intended post-mapping representation — the `$rhs` field in `Neura_AddOp` is defined as `Optional` in `NeuraOps.td` precisely to support it. However, `handleAddOp` in the interpreter unconditionally rejected any op with fewer than two SSA operands, making it impossible to interpret any fully mapped IR that contains `neura.add`.
This was observed when running `neura-interpreter` on the ReLU e2e mapped IR (`test/e2e/relu/Output/relu_kernel.mlir.tmp-mapping.mlir`), where the loop index increment `i + 1` maps to:
```mlir
%23 = "neura.add"(%22) {rhs_value = 1 : i64} : (!neura.data<i64, i1>) -> !neura.data<i64, i1>
```
PR Summary
Interpreter
Tests