Timing improvements and preliminary support for CDCs

[aehart]

This PR includes a couple updates to improve timing on FPGA1:

• Memory-specific signals are now used for all sync_nent ports. These signals already existed, but weren't used for some memories, so this update should reduce fanout for those signals.
• Pipelines were added for the BX signals going into the tf_merge_streamer modules, with a dedicated pipeline for each instance. Again, this should help reduce fanout for these signals, as well as adding extra shift registers so that they can traverse the FPGA over more clock cycles.

This PR also adds an extra clock port to the SectorProcessor so that both a 240- and 360-MHz clock can be plugged in. Both of these clocks are also generated in the test benches, although for now, only the 240-MHz clock is used.

Finally, the now-obsolete regceb port has been removed from the memory modules, and the delay argument has been removed from generator_hdl.py.