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Fixes to allow reduced FPGA1 project to run with agreement with emulation #75

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Merged
aehart merged 3 commits into from
Sep 9, 2025
Merged

Fixes to allow reduced FPGA1 project to run with agreement with emulation #75

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5721e35
Fixes to allow reduced FPGA1 project to run with agreement with emula…
Sep 1, 2025
6e2dc3c
Corrections so that VMSTE_PHIL don't ther CLC_CNT_INIT for IL memory
Sep 3, 2025
44de92c
Fixes for FPGA1 debug printout and ASInner module ordering
Sep 4, 2025
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4 changes: 3 additions & 1 deletion TrackletGraph.py
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Original file line number Diff line number Diff line change
Expand Up @@ -245,8 +245,10 @@ def populate_bitwidths(mem,hls_dir): # FIXME this information should be parsed f
if ( mem.mtype == "TrackletProjections" or mem.mtype == "VMProjections"
or mem.mtype == "CandidateMatch" or mem.mtype == "FullMatch" or mem.mtype == "VMStubsME"
or mem.mtype == "StubPairs" or mem.mtype == "VMStubsTEInner" or mem.mtype == "VMStubsTEOuter"
or mem.mtype == "InputLink" or mem.mtype == "DTCLink" or mem.mtype == "AllInnerStubs"):
or mem.mtype == "DTCLink" or mem.mtype == "AllInnerStubs"):
mem.bxbitwidth = 1
elif ( mem.mtype == "InputLink") :
mem.bxbitwidth = 2
elif ( mem.mtype == "AllProj"
or mem.mtype == "AllStubs" or mem.mtype == "TrackletParameters"):
mem.bxbitwidth = 3
Expand Down
25 changes: 23 additions & 2 deletions WriteHDLUtils.py
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Original file line number Diff line number Diff line change
Expand Up @@ -271,6 +271,27 @@ def getListsOfGroupedMemories(aProcModule):
memList = list(aProcModule.upstreams + aProcModule.downstreams)
portList = list(aProcModule.input_port_names + aProcModule.output_port_names)

#horrible hack to fix order of modules
ia=-1;
ib=-1;
for mem in memList:
if "_BE" in mem.var() :
ia=memList.index(mem);
if "_BF" in mem.var() :
ib=memList.index(mem);
if ia != -1 and ib != -1 and ib < ia :
memList[ia], memList[ib] = memList[ib], memList[ia]

ia=-1;
ib=-1;
for mem in memList:
if "L1PHIH_BC" in mem.var() :
ia=memList.index(mem);
if "L1PHIH_BD" in mem.var() :
ib=memList.index(mem);
if ia != -1 and ib != -1 and ib < ia :
memList[ia], memList[ib] = memList[ib], memList[ia]
Comment on lines +274 to +293
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@aehart aehart Sep 9, 2025

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@aryd I'm assuming the order here comes from the order in the wiring files, so should the order ultimately be fixed in the TrackletConfigBuilder in CMSSW? I'm not proposing doing this immediately, but it seems like it would be better to eventually fix the issue where it originates, if possible.


# Sort the VMSME and VMSTE using portList, first by the phi region number (e.g. 2 in "vmstuboutPHIA2"), then alphabetically
zipped_list = list(zip(memList, portList))
zipped_list.sort(key=lambda m_p: 0 if 'vmstubout' else int("".join([i for i in m_p[1] if i.isdigit()]))) # sort by number
Expand Down Expand Up @@ -1208,7 +1229,7 @@ def writeModuleInst_generic(module, hls_src_dir, f_writeTemplatePars,
str_ctrl_func = ""
oneProcUpMem = None
for mem in module.upstreams:
if mem.bxbitwidth != 1: continue
if mem.bxbitwidth != 1 and mem.bxbitwidth != 2: continue #What is this doing?
if mem.upstreams[0] is None: continue
oneProcUpMem = mem
break
Expand Down Expand Up @@ -1255,7 +1276,7 @@ def writeModuleInst_generic(module, hls_src_dir, f_writeTemplatePars,
# bunch crossing
if argtype == "BXType":
for mem in module.upstreams:
if mem.bxbitwidth != 1: continue
if mem.bxbitwidth != 1 and mem.bxbitwidth != 2: continue #FIXME what is this doing
if mem.is_initial:
string_bx_in += writeProcBXPort(module.inst,True,True,first_of_type,delay)
break
Expand Down
14 changes: 11 additions & 3 deletions WriteVHDLSyntax.py
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Original file line number Diff line number Diff line change
Expand Up @@ -712,8 +712,6 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
portlist += " doutb => "+mem+"_V_dout,\n"
if "AS" in mem and "n1" in mem and split == 1:
portlist += " sync_nent => "+first_tp+"_start,\n"
elif "TPAR" in mem and split == 1:
portlist += " sync_nent => TP_done,\n"
else:
portlist += " sync_nent => "+mem+"_start,\n"
if memmod.has_numEntries_out or ("n1" in mem and split == 1):
Expand Down Expand Up @@ -1296,7 +1294,9 @@ def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_bi
string_mem += " write"+mem+" : entity work.FileWriterFIFO\n"
string_mem += " generic map (\n"
string_mem += " FILE_NAME".ljust(str_len)+"=> FILE_OUT_"+mtypeB+"&\""+mem+"\"&outputFileNameEnding,\n"
string_mem += " FIFO_WIDTH".ljust(str_len)+"=> " + str(width) + "\n"
string_mem += " FIFO_WIDTH".ljust(str_len)+"=> " + str(width) + ",\n"
string_mem += " BX_CNT_INIT".ljust(str_len)+"=> -1,\n"
string_mem += " DONE_DELAY".ljust(str_len)+"=> 6\n"
string_mem += " )\n"
string_mem += " port map (\n"
string_mem += " CLK".ljust(str_len)+"=> CLK,\n"
Expand All @@ -1318,12 +1318,18 @@ def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_bi
string_mem += " PAGE_LENGTH".ljust(str_len)+"=> 1024,\n"
if "VMSME" in mem:
string_mem += " CLK_CNT_INIT".ljust(str_len)+"=> -21,\n" #-21 is emperically determined to allign the FileWriter BX with the data stream
if "VMSTE" in mem:
string_mem += " CLK_CNT_INIT".ljust(str_len)+"=> -17,\n" #-17 is emperically determined to allign the FileWriter BX with the data stream
if "MPROJ" in mem :
string_mem += " NUM_TPAGES".ljust(str_len)+"=> 4,\n"
string_mem += " PAGE_LENGTH".ljust(str_len)+"=> 64,\n"
string_mem += " CLK_CNT_INIT".ljust(str_len)+"=> -21,\n" #-21 is emperically determined to allign the FileWriter BX with the data stream
if "FM" in mem :
string_mem += " CLK_CNT_INIT".ljust(str_len)+"=> -21,\n" #-21 is emperically determined to allign the FileWriter BX with the data stream
if "IL_" in mem :
string_mem += " CLK_CNT_INIT".ljust(str_len)+"=> -8,\n" #-8 is emperically determined to allign the FileWriter BX with the data stream
if "AS" in mem :
string_mem += " CLK_CNT_INIT".ljust(str_len)+"=> -17,\n" #-17 is emperically determined to allign the FileWriter BX with the data stream changed for FPGA1 project
string_mem += " NUM_PAGES".ljust(str_len)+"=> " + str(2**bxbitwidth) + "\n"
string_mem += " )\n"
string_mem += " port map (\n"
Expand Down Expand Up @@ -1377,6 +1383,8 @@ def writeTBMemoryWriteRAMInstance(mtypeB, memDict, proc, bxbitwidth, is_binned,
string_mem += " write"+mem+" : entity work.FileWriterFIFO\n"
string_mem += " generic map (\n"
string_mem += " FILE_NAME".ljust(str_len)+"=> FILE_OUT_"+mtypeB+"&\""+mem+"\"&outputFileNameEnding,\n"
string_mem += " BX_CNT_INIT".ljust(str_len)+"=> -1,\n"
string_mem += " DONE_DELAY".ljust(str_len)+"=> 5,\n"
string_mem += " FIFO_WIDTH".ljust(str_len)+"=> " + str(width) + "\n"
string_mem += " )\n"
string_mem += " port map (\n"
Expand Down