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Pipelining reset #71

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Merged
aehart merged 1 commit into from
Jun 16, 2025
Merged

Pipelining reset #71

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4 changes: 4 additions & 0 deletions WriteVHDLSyntax.py
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Original file line number Diff line number Diff line change
Expand Up @@ -636,6 +636,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
portlist += " dina => "+mem+"_din,\n"
if delay > 0:
delay_portlist += " clk => clk,\n"
delay_portlist += " reset => reset,\n"
delay_portlist += " wea => "+mem+"_wea,\n"
delay_portlist += " addra => "+mem+"_writeaddr,\n"
delay_portlist += " dina => "+mem+"_din,\n"
Expand Down Expand Up @@ -1529,6 +1530,7 @@ def writeStartSwitchAndInternalBX(module,mem,extraports=False, delay = 0, first_

int_ctrl_func += " port map (\n"
int_ctrl_func += " clk => clk,\n"
int_ctrl_func += " reset => reset,\n"
int_ctrl_func += " done => PC_start,\n"
int_ctrl_func += " bx_out => PC_bx_in,\n"
int_ctrl_func += " bx => PC_bx_out,\n"
Expand All @@ -1549,6 +1551,7 @@ def writeStartSwitchAndInternalBX(module,mem,extraports=False, delay = 0, first_
int_ctrl_func += " LATCH_"+mtype+": entity work.tf_pipeline_slr_xing\n"
int_ctrl_func += " port map (\n"
int_ctrl_func += " clk => clk,\n"
int_ctrl_func += " reset => reset,\n"
if "MP_" in mtype :
int_ctrl_func += " done => PC_done,\n"
int_ctrl_func += " bx_out => PC_bx_out,\n"
Expand All @@ -1573,6 +1576,7 @@ def writeStartSwitchAndInternalBX(module,mem,extraports=False, delay = 0, first_
int_ctrl_func += " LATCH_"+mtype+"_BX_GEN: entity work.tf_pipeline_slr_xing\n"
int_ctrl_func += " port map (\n"
int_ctrl_func += " clk => clk,\n"
int_ctrl_func += " reset => reset,\n"
if first_proc:
if mtype_up == "VMSMER":
mtype_up = "PC"
Expand Down