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Small change to pick correct TP for reduced FPGA1 project #70

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Merged
aehart merged 2 commits into from
Jun 4, 2025
Merged

Small change to pick correct TP for reduced FPGA1 project #70

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d431ebc
Small change to pick correct TP for reduced FPGA1 project - old code …
Apr 24, 2025
3a6495b
Fix typos
Jun 4, 2025
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13 changes: 12 additions & 1 deletion WriteVHDLSyntax.py
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Original file line number Diff line number Diff line change
Expand Up @@ -439,6 +439,17 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl

first_merge_streamer = True

first_tp=""

for memmod in memList:
mem=memmod.inst
if "L1L2" in mem:
first_tp = "TP_L1L2A"

#If we did not find L1L2 assume L5L6 for reduced project
if first_tp == "" :
first_tp = "TP_L5L6A"

for memmod in memList:

nmem = 0
Expand Down Expand Up @@ -747,7 +758,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
if "MPAR" in mem and "in" not in mem:
portlist += " sync_nent => "+mem+"_start,\n"
elif "AS" in mem and "n1" in mem and split == 1:
portlist += " sync_nent => TP_L1L2A_start,\n"
portlist += " sync_nent => "+first_tp+"_start,\n"
elif "TPAR" in mem and split == 1:
portlist += " sync_nent => TP_done,\n"
else:
Expand Down