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Merged
aehart merged 14 commits into from
Mar 25, 2025
Merged

Multiple MPs + Reduced split configuration + VM stub memory optimization #68

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d360074
Add new bodge files for AAAA and BBBB track builders - I think eventu…
Dec 7, 2024
9c2713b
Remove the 'bodge' files as no longer needed
Dec 8, 2024
5a08387
Remove the 'bodge' files as no longer needed
Dec 8, 2024
bba0f12
Minor logic fix in string parsing
Dec 14, 2024
7cfb7e0
Changes so that each trackword has all layers
Jan 28, 2025
03d0072
Changes so that each trackword has all layers
Jan 28, 2025
a47e0a6
Updates for new bin mask interface in VMStub memories
Feb 10, 2025
f6a2805
Fix review comments to remove some hardcoded values
Feb 12, 2025
8d21fea
Updates in WriteVHDLSyntax to write correct memory page size for the …
Feb 25, 2025
4ac45bc
Various fixes for BX alignment to get agreement for reduced project w…
Mar 2, 2025
7e1b9b7
Fix PR comments from A. Hart
Mar 2, 2025
21fdb11
Fix to use the hit mask for the mpar memory
Mar 8, 2025
c9c1de5
Correct calculation of number of stub words for writing TB memories
Mar 9, 2025
de1050e
Fixes to writing of debug files
Mar 10, 2025
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14 changes: 3 additions & 11 deletions TrackletGraph.py
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Original file line number Diff line number Diff line change
Expand Up @@ -233,7 +233,7 @@ def populate_bitwidths(mem,hls_dir): # FIXME this information should be parsed f
if barrelPS>-1 or barrel2S>-1: mem.bitwidth = 52
if disk>-1: mem.bitwidth = 55
elif mem.mtype == "TrackWord":
mem.bitwidth = 104
mem.bitwidth = 113
elif mem.mtype == "BarrelStubWord":
mem.bitwidth = 46
elif mem.mtype == "DiskStubWord":
Expand Down Expand Up @@ -497,16 +497,8 @@ def split_track_fit_streams(p_dict, m_dict):
down_p.upstreams.append(new_mem)
down_p.input_port_names.append("trackwordin")

# Determine the layers/disks from the associated full match
# memories.
layers = set()
if up_p is not None:
for up_m in up_p.upstreams:
if up_m.mtype != "FullMatch":
continue
layer = up_m.inst.split("_")[-1][0:2]
assert(layer.startswith("L") or layer.startswith("D"))
layers.add(layer)
# We will have all layers for each TrackWord
layers = {'L6', 'D5', 'L4', 'D2', 'D1', 'L2', 'L5', 'L1', 'L3', 'D4', 'D3'}

# Replace the old memory with a stub word for each of the
# layers/disks that can have matches.
Expand Down
82 changes: 46 additions & 36 deletions WriteVHDLSyntax.py
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Original file line number Diff line number Diff line change
Expand Up @@ -202,6 +202,8 @@ def writeTBMemoryReadInstance(mtypeB, memDict, bxbitwidth, is_initial, is_binned
memtmp = memtmp.replace("n1","")
# memtmp = "T"+mem[1:10]
string_mem += " FILE_NAME".ljust(str_len) + "=> FILE_IN_" + mtypeB+"&\""+ memtmp + "\"&inputFileNameEnding,\n"
if "MPAR" in mem:
string_mem += " PAGE_LENGTH".ljust(str_len) + "=> 128,\n"
string_mem += " DELAY".ljust(str_len) + "=> " + mtypeB.split("_")[0] + "_DELAY*MAX_ENTRIES,\n"
string_mem += " RAM_WIDTH".ljust(str_len) + "=> " + mtypeB.split("_")[1] + ",\n"
string_mem += " NUM_PAGES".ljust(str_len) + "=> " + str(2**bxbitwidth) + ",\n"
Expand Down Expand Up @@ -317,6 +319,7 @@ def writeMemoryUtil(memDict, memInfoDict):
if "MPAR" in mtypeB:
tName = "t_"+mtypeB+"_ADDR"
ss += " subtype "+tName+" is std_logic_vector("+str(8+memInfo.bxbitwidth)+" downto 0);\n"
#ss += " subtype "+tName+" is std_logic_vector("+str(7+memInfo.bxbitwidth)+" downto 0);\n"
elif "MPROJ" in mtypeB:
tName = "t_"+mtypeB+"_ADDR"
ss += " subtype "+tName+" is std_logic_vector("+str(7+memInfo.bxbitwidth)+" downto 0);\n"
Expand Down Expand Up @@ -346,6 +349,15 @@ def writeMemoryUtil(memDict, memInfoDict):
tName = "t_"+mtypeB+"_NENTADDRDISK"
nentaddrbits = "4"
ss += " subtype "+tName+" is std_logic_vector("+nentaddrbits+" downto 0);\n"
#FIXME - hardcoded number
tName = "t_"+mtypeB+"_ADDRBINMASK"
ss += " subtype "+tName+" is std_logic_vector(3 downto 0);\n"
tName = "t_"+mtypeB+"_ADDRBINMASKDISK"
ss += " subtype "+tName+" is std_logic_vector(4 downto 0);\n"
tName = "t_"+mtypeB+"_BINMASK"
ss += " subtype "+tName+" is std_logic_vector(7 downto 0);\n"
tName = "t_"+mtypeB+"_BINMASKDISK"
ss += " subtype "+tName+" is std_logic_vector(7 downto 0);\n"
else:
#FIXME
tpages = 1
Expand Down Expand Up @@ -544,6 +556,18 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
wirelist += "t_"+mtypeB+"_DATA_"+str(nmem)+";\n"
wirelist += " signal "+mem+"_V_masktmp : "
wirelist += "t_"+mtypeB+"_MASK"+disk+"_"+str(num_pages)+";\n"
wirelist += " signal "+mem+"_V_addr_binmaskA : "
wirelist += "t_"+mtypeB+"_ADDRBINMASK"+disk+";\n"
wirelist += " signal "+mem+"_V_binmaskA : "
wirelist += "t_"+mtypeB+"_BINMASK"+disk+";\n"
wirelist += " signal "+mem+"_enb_binmaskA : "
wirelist += "t_"+mtypeB+"_1b;\n"
wirelist += " signal "+mem+"_V_addr_binmaskB : "
wirelist += "t_"+mtypeB+"_ADDRBINMASK"+disk+";\n"
wirelist += " signal "+mem+"_V_binmaskB : "
wirelist += "t_"+mtypeB+"_BINMASK"+disk+";\n"
wirelist += " signal "+mem+"_enb_binmaskB : "
wirelist += "t_"+mtypeB+"_1b;\n"
else:
wirelist += " signal "+mem+"_AV_dout_nent : "
wirelist += "t_"+mtypeB+"_NENT; -- (#page)\n"
Expand All @@ -563,8 +587,10 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
# Write parameters
parameterlist += " RAM_WIDTH => "+bitwidth+",\n"
parameterlist += " NUM_PAGES => "+str(num_pages)+",\n"
if "MPROJ" in mem:
if "MPROJ" in mem :
parameterlist += " PAGE_LENGTH => 64,\n"
if "MPAR" in mem:
parameterlist += " PAGE_LENGTH => 128,\n"
if "MPROJ" in mem or "MPAR" in mem:
parameterlist += " NUM_TPAGES => 4,\n"
parameterlist += " INIT_FILE => \"\",\n"
Expand Down Expand Up @@ -746,7 +772,12 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
portlist += " enb_nent => "+mem+"_enb_nent,\n"
portlist += " addr_nent => "+mem+"_V_addr_nent,\n"
portlist += " dout_nent => "+mem+"_AV_dout_nent,\n"
portlist += " mask_o => "+mem+"_V_masktmp,\n"
portlist += " enb_binmaska => "+mem+"_enb_binmaska,\n"
portlist += " addr_binmaska => "+mem+"_V_addr_binmaska,\n"
portlist += " binmaska_o => "+mem+"_V_binmaska,\n"
portlist += " enb_binmaskb => "+mem+"_enb_binmaskb,\n"
portlist += " addr_binmaskb => "+mem+"_V_addr_binmaskb,\n"
portlist += " binmaskb_o => "+mem+"_V_binmaskb,\n"
else:
portlist += " nent_o => "+mem+"_AV_dout_nent,\n"
if "MPROJ" in mem:
Expand All @@ -768,18 +799,6 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
else:
mem_str += " dataout"+str(i)+" => "+mem+"_AV_dout("+str(i)+")\n"
mem_str += " );\n\n"
disk = ""
if "VMSME_D" in mem:
disk = "DISK"
mem_str += " "+mem+"_maskformat : entity work.vmstub"+str(nbx)+"mask"+disk+"\n"
mem_str += " port map (\n"
mem_str += " datain => "+mem+"_V_masktmp,\n"
for i in range(0, nbx) :
if i < nbx-1 :
mem_str += " dataout"+str(i)+" => "+mem+"_AV_dout_mask("+str(i)+"),\n"
else:
mem_str += " dataout"+str(i)+" => "+mem+"_AV_dout_mask("+str(i)+")\n"
mem_str += " );\n\n"
mem_str += " "+mem+" : entity work.tf_mem_bin\n"
else:
if "MPROJ" in mem:
Expand Down Expand Up @@ -825,7 +844,7 @@ def writeControlSignals_interface(initial_proc, final_procs, notfinal_procs, del
string_ctrl_signals += " "+final_proc_short+"_bx_out : out std_logic_vector(2 downto 0);\n"
string_ctrl_signals += " "+final_proc_short+"_bx_out_vld : out std_logic;\n"
string_ctrl_signals += " "+final_proc_short+"_done : out std_logic;\n"
if final_proc_short == "FT":
if final_proc_short == "TB":
for final_proc in final_procs:
string_ctrl_signals += " "+final_proc+"_last_track : out std_logic;\n"
string_ctrl_signals += " "+final_proc+"_last_track_vld : out std_logic;\n"
Expand Down Expand Up @@ -916,7 +935,6 @@ def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict, split, MPARdict = 0)
string_output_mems += " "+mem+"_A_enb : in t_"+mtypeB+"_A1b;\n"
string_output_mems += " "+mem+"_AV_readaddr : in t_"+mtypeB+"_AADDR"+disk+";\n"
string_output_mems += " "+mem+"_AV_dout : out t_"+mtypeB+"_ADATA;\n"
string_output_mems += " "+mem+"_AV_dout_mask : out t_"+mtypeB+"_MASK"+disk+";\n"
string_output_mems += " "+mem+"_enb_nent : out t_"+mtypeB+"_1b;\n"
string_output_mems += " "+mem+"_V_addr_nent : out t_"+mtypeB+"_NENTADDR"+disk+";\n"
string_output_mems += " "+mem+"_AV_dout_nent : out t_"+mtypeB+"_NENT;\n"
Expand All @@ -937,8 +955,6 @@ def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict, split, MPARdict = 0)
if memInfo.is_binned:
string_output_mems += " "+mem+"_AV_dout_nent : "
string_output_mems += "out t_"+mtypeB+"_NENT;\n"
string_output_mems += " "+mem+"_AV_dout_mask : "
string_output_mems += "out t_"+mtypeB+"_MASK;\n"
else:
string_output_mems += " "+mem+"_AV_dout_nent : "
string_output_mems += "out t_"+mtypeB+"_NENT;\n"
Expand Down Expand Up @@ -1071,7 +1087,7 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi
string_ctrl_signals += (" signal "+final_procs[-1].mtype_short()+"_bx_out").ljust(str_len)+": std_logic_vector(2 downto 0) := (others => '1');\n"
string_ctrl_signals += (" signal "+final_procs[-1].mtype_short()+"_bx_out_vld").ljust(str_len)+": std_logic := '0';\n"
string_ctrl_signals += (" signal "+final_procs[-1].mtype_short()+"_done").ljust(str_len)+": std_logic := '0';\n"
if final_procs[-1].mtype_short().startswith("FT"):
if final_procs[-1].mtype_short().startswith("TB"):
for final_proc in final_procs:
string_ctrl_signals += (" signal "+final_proc.inst+"_last_track").ljust(str_len)+": std_logic := '0';\n"
string_ctrl_signals += (" signal "+final_proc.inst+"_last_track_vld").ljust(str_len)+": std_logic := '0';\n"
Expand Down Expand Up @@ -1138,8 +1154,6 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi
string_ctrl_signals += ("t_"+mtypeB+"_ADATA").ljust(str_len2)+":= (others => (others => '0'));\n"
string_ctrl_signals += (" signal "+mem+"_AAV_dout_nent").ljust(str_len)+": "
string_ctrl_signals += ("t_"+mtypeB+"_NENT").ljust(str_len2)+":= (others => '0'); -- (#page)(#bin)\n"
string_ctrl_signals += (" signal "+mem+"_AV_dout_mask").ljust(str_len)+": "
string_ctrl_signals += ("t_"+mtypeB+"_MASK").ljust(str_len2)+":= (others => (others => '0')); -- (#page)(#bin)\n"
elif split == 1 and "TPAR" in mem:
seed = mem.split("_")[1][:-1]
itc = mem.split("_")[1][-1]
Expand Down Expand Up @@ -1219,7 +1233,7 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc
string_fwblock_inst += (" " + final_procs[-1].mtype_short() + "_bx_out").ljust(str_len) + "=> " + final_procs[-1].mtype_short() + "_bx_out,\n"
string_fwblock_inst += (" " + final_procs[-1].mtype_short() + "_bx_out_vld").ljust(str_len) + "=> " + final_procs[-1].mtype_short() + "_bx_out_vld,\n"
string_fwblock_inst += (" " + final_procs[-1].mtype_short() + "_done").ljust(str_len) + "=> " + final_procs[-1].mtype_short() + "_done,\n"
if final_procs[-1].mtype_short().startswith("FT"):
if final_procs[-1].mtype_short().startswith("TB"):
for final_proc in final_procs :
string_fwblock_inst += (" " + final_proc.inst + "_last_track").ljust(str_len) + "=> " + final_proc.inst + "_last_track,\n"
string_fwblock_inst += (" " + final_proc.inst + "_last_track_vld").ljust(str_len) + "=> " + final_proc.inst + "_last_track_vld,\n"
Expand Down Expand Up @@ -1271,7 +1285,7 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc
string_output += (" "+mem+"_A_enb").ljust(str_len) + "=> "+mem+"_enb,\n"
string_output += (" "+mem+"_AV_readaddr").ljust(str_len) + "=> "+mem+"_readaddr,\n"
string_output += (" "+mem+"_AV_dout").ljust(str_len) + "=> "+mem+"_dout,\n"
string_output += (" "+mem+"_AV_dout_mask").ljust(str_len) + "=> open,\n" #FIXME
#string_output += (" "+mem+"_AV_dout_mask").ljust(str_len) + "=> open,\n" #FIXME
string_output += (" "+mem+"_enb_nent").ljust(str_len) + "=> open,\n"
string_output += (" "+mem+"_V_addr_nent").ljust(str_len) + "=> open,\n"
string_output += (" "+mem+"_AV_dout_nent").ljust(str_len) + "=> open,\n"
Expand Down Expand Up @@ -1360,7 +1374,7 @@ def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_bi
string_mem += " ADDR".ljust(str_len)+"=> "+mem+"_writeaddr,\n"
string_mem += " DATA".ljust(str_len)+"=> "+mem+"_din,\n"
string_mem += " WRITE_EN".ljust(str_len)+"=> "+mem+"_wea,\n"
if proc == "VMSMER" :
if proc == "VMSMER" or proc == "PC":
string_mem += " START".ljust(str_len)+"=> PC_START,\n"
else:
string_mem += " START".ljust(str_len)+"=> "+(proc+"_START,\n" if not proc_up else proc_up+"_DONE,\n")
Expand Down Expand Up @@ -1480,6 +1494,7 @@ def writeProcCombination(module, str_ctrl_func, str_ports):
if "PC_" in module.inst:
module_str += " " + module.inst + "_mem_reader : entity work.mem_reader\n"
module_str += " generic map (\n"
module_str += " PAGE_LENGTH => 128,\n"
module_str += " RAM_WIDTH => " + str(module.upstreams[0].bitwidth) + ",\n"
module_str += " NUM_TPAGES => 4,\n"
module_str += " NAME => \""+module.inst+"_mem_reader\"\n"
Expand Down Expand Up @@ -1643,7 +1658,7 @@ def writeProcBXPort(modName,isInput,isInitial,first_of_type,delay):
else:
if first_of_type and not ("VMSMER" in modName or "PC" in modName):
bx_str += " bx_o_V => "+modName.split("_")[0]+"_bx_out,\n"
if ("FT_" in modName) or ("TP_" in modName):
if ("TB_" in modName) or ("TP_" in modName):
bx_str += " bx_o_V_ap_vld => "+modName.split("_")[0]+"_bx_out_vld,\n"
else:
bx_str += " bx_o_V_ap_vld => open,\n"
Expand Down Expand Up @@ -1735,17 +1750,12 @@ def writeProcMemoryRHSPorts(argname,mem,portindex=0, split = 0):
string_mem_ports += " "+argname+"_nentries_V_ce0 => "+mem.mtype_short()+"_"+mem.var()+"_enb_nent,\n"
string_mem_ports += " "+argname+"_nentries_V_address0 => "+mem.mtype_short()+"_"+mem.var()+"_V_addr_nent,\n"
string_mem_ports += " "+argname+"_nentries_V_q0 => "+mem.mtype_short()+"_"+mem.var()+"_AV_dout_nent,\n"
for i in range(0,2**mem.bxbitwidth):
nrz = 8
if mem.var()[0] == "D" and split == 2:
nrz = 16
for j in range(0,nrz):
string_mem_ports += " "+argname+"_binmask8_"+str(i)+"_V_"+str(j)+" => ("
for k in range(0,8):
if k != 0 :
string_mem_ports += ", "
string_mem_ports += mem.mtype_short()+"_"+mem.var()+"_AV_dout_mask("+str(i)+")("+str((j+1)*8-k-1)+")"
string_mem_ports += "),\n"
string_mem_ports += " "+argname+"_binmaskA_V_address0 => "+mem.mtype_short()+"_"+mem.var()+"_V_addr_binmaskA,\n"
string_mem_ports += " "+argname+"_binmaskA_V_ce0 => "+mem.mtype_short()+"_"+mem.var()+"_enb_binmaskA,\n"
string_mem_ports += " "+argname+"_binmaskA_V_q0 => "+mem.mtype_short()+"_"+mem.var()+"_V_binmaskA,\n"
string_mem_ports += " "+argname+"_binmaskB_V_address0 => "+mem.mtype_short()+"_"+mem.var()+"_V_addr_binmaskB,\n"
string_mem_ports += " "+argname+"_binmaskB_V_ce0 => "+mem.mtype_short()+"_"+mem.var()+"_enb_binmaskB,\n"
string_mem_ports += " "+argname+"_binmaskB_V_q0 => "+mem.mtype_short()+"_"+mem.var()+"_V_binmaskB,\n"
else:
tpage = 1
if "MPROJ" in mem.mtype_short() :
Expand Down
16 changes: 0 additions & 16 deletions bodge/TF_D1D2_tb_writer.vhd.bodge
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15 changes: 0 additions & 15 deletions bodge/TF_D3D4_tb_writer.vhd.bodge
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15 changes: 0 additions & 15 deletions bodge/TF_L1D1_tb_writer.vhd.bodge
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15 changes: 0 additions & 15 deletions bodge/TF_L1L2_tb_writer.vhd.bodge
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15 changes: 0 additions & 15 deletions bodge/TF_L2D1_tb_writer.vhd.bodge
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