Preliminary CDC support

IntegrationTests/CombinedConfig_FPGA1/script/makeProject.tcl

@@ -171,6 +171,10 @@ add_files -fileset utils_1 [glob common/script/post.tcl]
 # Add HDL for TB
 add_files -fileset sim_1 [glob ../tb/tb_tf_top.vhd]
 
+# Add clock wizard IP for TB
+import_ip [glob common/ip/*.xci]
+upgrade_ip [get_ips clk_wiz_240_360]
+
 # Add constraints (clock etc.)
 add_files -fileset constrs_1 [glob common/hdl/constraints.xdc]
 add_files -fileset constrs_1 [glob soft_floorplan.xdc]
@@ -179,6 +183,7 @@ add_files -fileset constrs_1 [glob soft_floorplan.xdc]
 set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}]
 set_property top -value ${topLevelHDL} -objects [get_filesets sim_1]
 set_property top -value "tb_tf_top" -objects [get_filesets sim_1]
+set_property used_in_implementation false [get_files clk_wiz_240_360.xci]
 set_property xsim.simulate.runtime -value "0us" -objects  [get_filesets sim_1]
 
 # Set 'synth_1` fileset properties

IntegrationTests/CombinedConfig_FPGA1/script/runSim.tcl

@@ -5,6 +5,9 @@ open_project $projName/$projName.xpr
 set_property simulator_language VHDL [current_project]
 reset_simulation sim_1
 
+# Run OOC synthesis for clock wizard
+source ./common/script/synth_clk_wiz_240_360.tcl
+
 # Create directory for output .txt file
 file delete -force dataOut/
 file mkdir dataOut/

IntegrationTests/CombinedConfig_FPGA2/script/makeProject.tcl

@@ -157,6 +157,10 @@ add_files -fileset utils_1 [glob common/script/post.tcl]
 # Add HDL for TB
 add_files -fileset sim_1 [glob ../tb/tb_tf_top.vhd]
 
+# Add clock wizard IP for TB
+import_ip [glob common/ip/*.xci]
+upgrade_ip [get_ips clk_wiz_240_360]
+
 # Add constraints (clock etc.)
 add_files -fileset constrs_1 [glob common/hdl/constraints.xdc]
 add_files -fileset constrs_1 [glob floorplan.xdc]
@@ -166,6 +170,7 @@ add_files -fileset constrs_1 [glob soft_floorplan.xdc]
 set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}]
 set_property top -value ${topLevelHDL} -objects [get_filesets sim_1]
 set_property top -value "tb_tf_top" -objects [get_filesets sim_1]
+set_property used_in_implementation false [get_files clk_wiz_240_360.xci]
 set_property xsim.simulate.runtime -value "0us" -objects  [get_filesets sim_1]
 
 # Set 'synth_1` fileset properties

IntegrationTests/CombinedConfig_FPGA2/script/runSim.tcl

@@ -5,6 +5,9 @@ open_project $projName/$projName.xpr
 set_property simulator_language VHDL [current_project]
 reset_simulation sim_1
 
+# Run OOC synthesis for clock wizard
+source ./common/script/synth_clk_wiz_240_360.tcl
+
 # Create directory for output .txt file
 file delete -force dataOut/
 file mkdir dataOut/

IntegrationTests/DualFPGA/firmware/hdl/payload_f1.vhd

@@ -81,7 +81,10 @@ begin
   -----------------------------------------------------------------------------
   tf1_wrapper_1 : entity work.tf1_wrapper
     port map (
-      clk                      => clk_p,
+      -- FIXME: for now, the same 240 MHz clock goes to both ports; should be
+      -- updated with 360 MHz clock from EMP framework
+      clk240                   => clk_p,
+      clk360                   => clk_p,
       reset                    => sp_reset,
       IR_start                 => s_ir_start,
       IR_bx_in                 => s_bx,

IntegrationTests/DualFPGA/firmware/hdl/tf1_wrapper.vhd

@@ -26,7 +26,8 @@ use work.memUtil_aux_pkg_f1.all;
 
 entity tf1_wrapper is
   port (
-    clk                      : in  std_logic;
+    clk240                   : in  std_logic;
+    clk360                   : in  std_logic;
     reset                    : in  std_logic;
     IR_start                 : in  std_logic;
     IR_bx_in                 : in  std_logic_vector(2 downto 0);
@@ -47,7 +48,8 @@ begin  -- architecture rtl
 
   SectorProcessor_1 : entity work.SectorProcessor
     port map (
-      clk                            => clk,
+      clk240                         => clk240,
+      clk360                         => clk360,
       reset                          => reset,
       IR_start                       => IR_start,
       IR_bx_in                       => IR_bx_in,

IntegrationTests/DualFPGA/firmware/hdl/tf2_wrapper.vhd

@@ -62,7 +62,10 @@ begin  -- architecture rtl
 
   SectorProcessor_1 : entity work.SectorProcessor
     port map (
-      clk                     => clk,
+      -- Two clock ports are available on the SectorProcessor for FPGA2,
+      -- although only the 240-MHz clock is currently used.
+      clk240                  => clk,
+      clk360                  => clk,
       reset                   => reset,
       PC_start                => PC_start,
       PC_bx_in                => PC_bx_in,

IntegrationTests/ReducedCombinedConfig_FPGA1/script/makeProject.tcl

@@ -96,6 +96,10 @@ remove_files -fileset sources_1 [glob common/hdl/tf_mem_new.vhd]
 # Add HDL for TB
 add_files -fileset sim_1 [glob ../tb/tb_tf_top.vhd]
 
+# Add clock wizard IP for TB
+import_ip [glob common/ip/*.xci]
+upgrade_ip [get_ips clk_wiz_240_360]
+
 # Add constraints (clock etc.)
 add_files -fileset constrs_1 [glob common/hdl/constraints.xdc]
 add_files -fileset constrs_1 [glob soft_floorplan.xdc]
@@ -104,6 +108,7 @@ add_files -fileset constrs_1 [glob soft_floorplan.xdc]
 set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}]
 set_property top -value ${topLevelHDL} -objects [get_filesets sim_1]
 set_property top -value "tb_tf_top" -objects [get_filesets sim_1]
+set_property used_in_implementation false [get_files clk_wiz_240_360.xci]
 set_property xsim.simulate.runtime -value "0us" -objects  [get_filesets sim_1]
 
 update_compile_order -fileset sources_1 

IntegrationTests/ReducedCombinedConfig_FPGA1/script/runSim.tcl

@@ -5,6 +5,9 @@ open_project $projName/$projName.xpr
 set_property simulator_language VHDL [current_project]
 reset_simulation sim_1
 
+# Run OOC synthesis for clock wizard
+source ./common/script/synth_clk_wiz_240_360.tcl
+
 # Create directory for output .txt file
 file delete -force dataOut/
 file mkdir dataOut/

IntegrationTests/ReducedCombinedConfig_FPGA2/script/makeProject.tcl

@@ -72,6 +72,10 @@ remove_files -fileset sources_1 [glob common/hdl/tf_mem_new.vhd]
 # Add HDL for TB
 add_files -fileset sim_1 [glob ../tb/tb_tf_top.vhd]
 
+# Add clock wizard IP for TB
+import_ip [glob common/ip/*.xci]
+upgrade_ip [get_ips clk_wiz_240_360]
+
 # Add constraints (clock etc.)
 add_files -fileset constrs_1 [glob common/hdl/constraints.xdc]
 add_files -fileset constrs_1 [glob floorplan.xdc]
@@ -81,6 +85,7 @@ add_files -fileset constrs_1 [glob soft_floorplan.xdc]
 set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}]
 set_property top -value ${topLevelHDL} -objects [get_filesets sim_1]
 set_property top -value "tb_tf_top" -objects [get_filesets sim_1]
+set_property used_in_implementation false [get_files clk_wiz_240_360.xci]
 set_property xsim.simulate.runtime -value "0us" -objects  [get_filesets sim_1]
 
 update_compile_order -fileset sources_1 

IntegrationTests/ReducedCombinedConfig_FPGA2/script/runSim.tcl

@@ -5,6 +5,9 @@ open_project $projName/$projName.xpr
 set_property simulator_language VHDL [current_project]
 reset_simulation sim_1
 
+# Run OOC synthesis for clock wizard
+source ./common/script/synth_clk_wiz_240_360.tcl
+
 # Create directory for output .txt file
 file delete -force dataOut/
 file mkdir dataOut/

IntegrationTests/common/hdl/FileReader.vhd

@@ -26,7 +26,6 @@ entity FileReader is
   generic (
     FILE_NAME   : string;   --! Name of .txt file corresponding to memory content
     PAGE_LENGTH : natural := PAGE_LENGTH; --! Page size
-    DELAY       : natural := 0;     --! Delay output signals by this many clocks.
     RAM_WIDTH   : natural := 18;    --! RAM data width
     NUM_PAGES   : natural := 2;     --! Number of pages in RAM memory
     NUM_TPAGES  : natural := 1;     --! Number of bins in RAM memory (1 if unbinned)
@@ -40,6 +39,7 @@ entity FileReader is
   );
   port (
     CLK      : in  std_logic;
+    LOCKED   : in  std_logic;
     ADDR     : out std_logic_vector(ADDR_WIDTH-1 downto 0);
     DATA     : out std_logic_vector(RAM_WIDTH-1 downto 0);
     START    : out std_logic;
@@ -221,14 +221,10 @@ end process procFile;
 
 procDelay : process(CLK)
   -- Process to delay start of first event output by required amount.   
-  variable COUNT : natural := 0;
 begin
 
   if rising_edge(CLK) then
-    if (COUNT < DELAY) then
-      COUNT := COUNT + 1;
-      WAITING <= true;
-    else
+    if (LOCKED = '1') then
       WAITING <= false;
     end if;
   end if;

IntegrationTests/common/hdl/FileReaderFIFO.vhd

@@ -25,13 +25,14 @@ use work.tf_pkg.all;
 entity FileReaderFIFO is
   generic (
     FILE_NAME  : string;   --! Name of .txt file corresponding to memory content
-    DELAY      : natural := 0;     --! Delay output signals by this many clocks.
     FIFO_WIDTH  : natural := 39;    --! Data width
     DEBUG      : boolean := false; --! Debug printout
-    FILE_NAME_DEBUG : string  := ""  --! Name of .txt file for debug printout.
+    FILE_NAME_DEBUG : string  := ""; --! Name of .txt file for debug printout.
+    MAX_ENTRIES     : natural := MAX_ENTRIES --! Period in clock ticks for switching pages
   );
   port (
     CLK       : in  std_logic;
+    LOCKED    : in  std_logic;
     READ_EN : in std_logic;
     EMPTY_NEG : out std_logic;
     DATA      : out std_logic_vector(FIFO_WIDTH-1 downto 0);
@@ -201,15 +202,11 @@ end process procFile;
 
 
 procDelay : process(CLK)
-  -- Process to delay start of first event output by required amount.   
-  variable COUNT : natural := 0;
+  -- Process to delay start of first event output until clocks locked
 begin
 
   if rising_edge(CLK) then
-    if (COUNT < DELAY) then
-      COUNT := COUNT + 1;
-      WAITING <= true;
-    else
+    if (LOCKED = '1') then
       WAITING <= false;
     end if;
   end if;

IntegrationTests/common/hdl/constraints.xdc

@@ -1,3 +1,9 @@
 # 240 MHz
-create_clock -period 4.160 -name clk -waveform {0.000 2.080} [get_ports clk]
+create_clock -period 4.166 -name clk240 [get_ports clk240]
 
+# 360 MHz
+create_clock -period 2.777 -name clk360 [get_ports clk360]
+
+# Multicycle constraints from 360 to 240 MHz
+set_multicycle_path 2 -setup -start -from [get_clocks clk360] -to [get_clocks clk240]
+set_multicycle_path 1 -hold -from [get_clocks clk360] -to [get_clocks clk240]