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7605763
EMP FPGA1 builds and meets timing
mcoshiro Nov 5, 2024
b16bf82
Fixed some interface issues, full chain outputs tracks in simulation
mcoshiro Nov 6, 2024
6eb9990
Perfect (or nearly perfect?) agreement in F1 output
mcoshiro Dec 6, 2024
4feff94
Updated, unified, and robust-ified tools for EMP and TF word data man…
mcoshiro Dec 9, 2024
8fa2b91
Update make rules to reflect updates to python scripts
mcoshiro Dec 9, 2024
4c7f183
Debugging updates
mcoshiro Dec 17, 2024
2c40cd5
Various fixes so at least L5L6 now agrees between simulation and hard…
mcoshiro Feb 11, 2025
f3712c5
Fixes for full project simulation/hardware agreement, and some FPGA2 …
mcoshiro Feb 25, 2025
01366de
Updated for compatibility with merged TB and EMP v0.9.X
mcoshiro Apr 24, 2025
29da2e6
Update ip generator for compatibility
mcoshiro May 1, 2025
0566386
Added version of Anders' floorplan
mcoshiro May 6, 2025
21abfb6
Added dont_touch to write address pipelines.
aehart May 27, 2025
4b9c2e2
Added soft floorplan
mcoshiro Jun 3, 2025
02553a3
EMP-side compatibility updates
mcoshiro Jun 3, 2025
6f813a8
Fix memprints download bug
mcoshiro Jun 3, 2025
4f6c936
Adjust FPGA1 latency, fix typo in tf_to_kf.hdl, and workaround for we…
mcoshiro Jun 3, 2025
249ac8f
Removed manual resync in favor of auto-resync in FPGA2 updated output…
mcoshiro Jun 12, 2025
853168d
Update default floorplan for FPGA1 to soft version
mcoshiro Jun 13, 2025
d49968a
Adjust F2 latency for delay updates, fix F1 check script
mcoshiro Jun 13, 2025
fb00ed9
Add reset logic to F1 as well
mcoshiro Aug 28, 2025
270ec58
Small updates to latency, checker scripts, and add ip generation help…
mcoshiro Aug 31, 2025
c9f714c
Implement Andrew's comments and compatibility with rebase
mcoshiro Sep 18, 2025
389c28c
Small typo
mcoshiro Sep 21, 2025
aac81a8
Test FPGA1 build again
mcoshiro Sep 22, 2025
ab43a68
Update download.sh directory check again
mcoshiro Sep 23, 2025
ff314ca
Confirmed simulation still works after rebase, moved script
mcoshiro Oct 2, 2025
62d1f37
Added latency pragma to InputRouter.
aehart Oct 6, 2025
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18 changes: 6 additions & 12 deletions IntegrationTests/DualFPGA/firmware/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -6,11 +6,11 @@ input_file_fpga2 = mem/in_fpga2.txt
fpga1_hls_script_path = ../../CombinedConfig_FPGA1/script
fpga2_hls_script_path = ../../CombinedConfig_FPGA2/script

all: add_common_files $(core_file_fpga1) $(core_file_fpga2) hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj $(input_file_fpga1) $(input_file_fpga2) apollo_input_fpga1 apollo_input_fpga2
all: add_common_files $(core_file_fpga1) $(core_file_fpga2) hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj $(input_file_fpga1) $(input_file_fpga2)

fpga1: add_common_files $(core_file_fpga1) hdl_add_files_fpga1 xciCreation_fpga1 kfin_adj $(input_file_fpga1) apollo_input_fpga1
fpga1: add_common_files $(core_file_fpga1) hdl_add_files_fpga1 xciCreation_fpga1 kfin_adj $(input_file_fpga1)

fpga2: add_common_files $(core_file_fpga2) hdl_add_files_fpga2 xciCreation_fpga2 kfin_adj $(input_file_fpga2) apollo_input_fpga2
fpga2: add_common_files $(core_file_fpga2) hdl_add_files_fpga2 xciCreation_fpga2 kfin_adj $(input_file_fpga2)

$(core_dir):
@mkdir cgn mem
Expand Down Expand Up @@ -51,15 +51,9 @@ hdl_add_files_fpga2: $(core_file)
cd hdl; ln -s ../../../CombinedConfig_FPGA2/hdl/memUtil_pkg.vhd memUtil_pkg_f2.vhd

$(input_file_fpga1): $(core_dir)
@python3 scripts/convert_emData2EMP_Link.py -d mem/MemPrintsSplit/InputStubs -o $(input_file_fpga1)
@python3 scripts/generate_fpga1_input.py -i mem/MemPrintsSplit/ -o $(input_file_fpga1)

$(input_file_fpga2): $(core_dir)
@python3 scripts/convert_emData2EMP_Link_FPGA2.py -d mem/MemPrintsSplit/ -o $(input_file_fpga2)
@python3 scripts/generate_fpga2_input.py -i mem/MemPrintsSplit/ -o $(input_file_fpga2)

apollo_input_fpga1: $(input_file_fpga1)
@python3 scripts/split_emp_input.py -i $(input_file_fpga1) -o mem/in_fpga1_

apollo_input_fpga2: $(input_file_fpga2)
@python3 scripts/split_emp_input.py -i $(input_file_fpga2) -o mem/in_fpga2_

.PHONY: all fpga1 fpga2 add_common_files hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj apollo_input_fpga1 apollo_input_fpga2
.PHONY: all fpga1 fpga2 add_common_files hdl_add_files_fpga1 hdl_add_files_fpga2 xciCreation_fpga1 xciCreation_fpga2 kfin_adj
6 changes: 4 additions & 2 deletions IntegrationTests/DualFPGA/firmware/cfg/payload_f1.dep
Original file line number Diff line number Diff line change
Expand Up @@ -12,14 +12,16 @@ src conv_pkg_f1.vhd
include -c firmware-hls:KalmanFilter/common components.dep

#Track Builder dependencies
src common/hdl/CreateStartSignal.vhd
#src --vhdl2008 common/hdl/tf_lut.vhd
src --vhdl2008 common/hdl/tf_mem_bin.vhd
src --vhdl2008 common/hdl/tf_mem_format.vhd
src --vhdl2008 common/hdl/tf_mem.vhd
src --vhdl2008 common/hdl/tf_merge_streamer.vhd
src common/hdl/tf_pkg.vhd
src --vhdl2008 common/hdl/tf_pipe_delay.vhd
src --vhdl2008 common/hdl/pipelining.vhd

#Floorplan
src ../ucf/floorplan_f1.tcl

################
# Include Cores
Expand Down
3 changes: 1 addition & 2 deletions IntegrationTests/DualFPGA/firmware/cfg/payload_f2.dep
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,6 @@ include -c firmware-hls:KalmanFilter/tq components.dep
include -c firmware-hls:KalmanFilter/common components.dep

#Tracklet dependencies
src common/hdl/CreateStartSignal.vhd
#src --vhdl2008 common/hdl/tf_lut.vhd
src --vhdl2008 common/hdl/tf_mem_bin.vhd
src --vhdl2008 common/hdl/tf_mem_format.vhd
Expand All @@ -27,7 +26,7 @@ src --vhdl2008 common/hdl/tf_mem_tproj.vhd
src --vhdl2008 common/hdl/tf_mem_tpar.vhd
src --vhdl2008 common/hdl/mem_reader.vhd
src common/hdl/tf_pkg.vhd
src --vhdl2008 common/hdl/tf_pipe_delay.vhd
src --vhdl2008 common/hdl/pipelining.vhd

#Floorplan
src ../ucf/floorplan_f2.tcl
Expand Down
54 changes: 27 additions & 27 deletions IntegrationTests/DualFPGA/firmware/hdl/emp_project_decl_f1.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -19,43 +19,43 @@ package emp_project_decl is
constant CLOCK_AUX_DIV : clock_divisor_array_t := (18, 9, 4); -- Dividers of CLOCK_COMMON_RATIO * 40 MHz

-- Readdjust if latency changes for FPGA1 algorithm
constant PAYLOAD_LATENCY : integer := 140;
constant PAYLOAD_LATENCY : integer := 399;

-- F1 transmits to F2 on inter-fpga links
constant REGION_CONF : region_conf_array_t := (
0 => kDummyRegion, -- service c2c
1 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
2 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
3 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
1 => (no_mgt, no_buf, no_fmt, buf, csp25), -- fpga-fpga
2 => (no_mgt, no_buf, no_fmt, buf, csp25), -- fpga-fpga
3 => (no_mgt, no_buf, no_fmt, buf, csp25), -- fpga-fpga
4 => kDummyRegion, -- not routed
5 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
6 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
7 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
8 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
9 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
10 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
11 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
12 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
13 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
14 => (no_mgt, no_buf, no_fmt, buf, gty25), -- fpga-fpga
5 => (no_mgt, no_buf, no_fmt, buf, csp25), -- fpga-fpga
6 => (no_mgt, no_buf, no_fmt, buf, csp25), -- fpga-fpga
7 => (no_mgt, no_buf, no_fmt, buf, csp25), -- fpga-fpga
8 => (no_mgt, no_buf, no_fmt, buf, csp25), -- fpga-fpga
9 => (no_mgt, no_buf, no_fmt, buf, csp25), -- fpga-fpga
10 => (no_mgt, no_buf, no_fmt, buf, csp25), -- fpga-fpga
11 => (no_mgt, no_buf, no_fmt, buf, csp25), -- fpga-fpga
12 => (no_mgt, no_buf, no_fmt, buf, csp25), -- fpga-fpga
13 => (no_mgt, no_buf, no_fmt, buf, csp25), -- fpga-fpga
14 => (no_mgt, no_buf, no_fmt, buf, csp25), -- fpga-fpga
15 => kDummyRegion, -- not routed
------cross
----- all MGTs instantiated bidirectionally for now
16 => kDummyRegion, -- not routed
17 => (gty25, buf, no_fmt, buf, gty25), -- firefly
18 => (gty25, buf, no_fmt, buf, gty25), -- firefly
19 => (gty25, buf, no_fmt, buf, gty25), -- firefly
17 => (csp25, buf, no_fmt, no_buf, no_mgt), -- firefly
18 => (csp25, buf, no_fmt, no_buf, no_mgt), -- firefly
19 => (csp25, buf, no_fmt, no_buf, no_mgt), -- firefly
20 => kDummyRegion, -- not routed
21 => (gty25, buf, no_fmt, buf, gty25), -- firefly
22 => (gty25, buf, no_fmt, buf, gty25), -- firefly
23 => (gty25, buf, no_fmt, buf, gty25), -- firefly
24 => (gty25, buf, no_fmt, buf, gty25), -- firefly
25 => (gty25, buf, no_fmt, buf, gty25), -- firefly
26 => (gty25, buf, no_fmt, buf, gty25), -- firefly
27 => (gty25, buf, no_fmt, buf, gty25), -- firefly
28 => (gty25, buf, no_fmt, buf, gty25), -- firefly
29 => (gty25, buf, no_fmt, buf, gty25), -- firefly
30 => (gty25, buf, no_fmt, buf, gty25), -- firefly
21 => (csp25, buf, no_fmt, no_buf, no_mgt), -- firefly
22 => (csp25, buf, no_fmt, no_buf, no_mgt), -- firefly
23 => (csp25, buf, no_fmt, no_buf, no_mgt), -- firefly
24 => (csp25, buf, no_fmt, no_buf, no_mgt), -- firefly
25 => (csp25, buf, no_fmt, no_buf, no_mgt), -- firefly
26 => (csp25, buf, no_fmt, no_buf, no_mgt), -- firefly
27 => (csp25, buf, no_fmt, no_buf, no_mgt), -- firefly
28 => (csp25, buf, no_fmt, no_buf, no_mgt), -- firefly
29 => (csp25, buf, no_fmt, no_buf, no_mgt), -- firefly
30 => (csp25, buf, no_fmt, no_buf, no_mgt), -- firefly
31 => kDummyRegion, -- service tcds

others => kDummyRegion
Expand Down
31 changes: 15 additions & 16 deletions IntegrationTests/DualFPGA/firmware/hdl/emp_project_decl_f2.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -18,26 +18,25 @@ package emp_project_decl is
constant CLOCK_RATIO : integer := 6;
constant CLOCK_AUX_DIV : clock_divisor_array_t := (18, 9, 4); -- Dividers of CLOCK_COMMON_RATIO * 40 MHz

-- Only used by nullalgo
constant PAYLOAD_LATENCY : integer := 891; --was 823
constant PAYLOAD_LATENCY : integer := 711;

-- F2 receives from F1 on inter-fpga links
constant REGION_CONF : region_conf_array_t := (
0 => kDummyRegion, -- service c2c
1 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
2 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
3 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
4 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
5 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
6 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
7 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
8 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
9 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
10 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
1 => (csp25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
2 => (csp25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
3 => (csp25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
4 => (csp25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
5 => (csp25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
6 => (csp25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
7 => (csp25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
8 => (csp25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
9 => (csp25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
10 => (csp25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
11 => kDummyRegion, -- not routed
12 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
13 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
14 => (gty25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
12 => (csp25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
13 => (csp25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
14 => (csp25, buf, no_fmt, no_buf, no_mgt), -- fpga-fpga
15 => kDummyRegion, -- not routed
------cross
----- all MGTs instantiated bidirectionally for now
Expand All @@ -48,7 +47,7 @@ package emp_project_decl is
20 => kDummyRegion, -- not routed
21 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly
22 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly
23 => (no_mgt, no_buf, no_fmt, buf, gty25), -- firefly
23 => (no_mgt, no_buf, no_fmt, buf, csp25), -- firefly
24 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly
25 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly
26 => (no_mgt, no_buf, no_fmt, no_buf, no_mgt), -- firefly
Expand Down
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