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@aehart aehart commented Mar 25, 2025

This PR is split off of #356 from @aryd and includes fixes for the pylint warnings in the CI.

N.B.: This PR should be merged immediately before merging #356.

@aehart aehart force-pushed the aryd_pylint_fixes branch from 98104fd to 790dd27 Compare April 8, 2025 14:33
@aehart aehart merged commit 95883ed into MultipleMPs_ReducedSplit_VMStubMemOptimization Apr 8, 2025
@aehart aehart deleted the aryd_pylint_fixes branch April 8, 2025 14:33
aehart added a commit that referenced this pull request Apr 8, 2025
* First version of code to combine TBs from 8 -> 2

* Fix typo

* Fixes to MP to produce new combined FM

* Add new bodge files for the combined TBs

* Restore testing 100 events

* Remove the 'bodge' files as no longer needed

* Changes for building project with new combined TB

* Updated floorplan for new TrackBuilders

* Correction to script_TB.tcl file

* Some cleanup of the write_mem methods

* Fix TrackMerger so that it runs. Still need more TLC

* Restore TP barrel and disk masks

* Some further code cleanup

* Adding missing #include and add hack to work around vivado hard crash

* Fixes so that we reach II=1 on test benches - this involved some hacks around HLS limitations

* First steps towards supporting multiple MPs

* Minor logic fix in string parsing

* Generalize the TrackBuilder so that it can handle the duplicate MPs

* Correct mistake in scrpt_MP.tcl

* Add missing return for integration builds

* Updates to allow the integrated FPGA2 project to build

* Cleanup printout when running download.sh

* Correct typo

* Fix missing pragma for building integrated project

* Updated to fix problem with integrated project

* Update to use new test vectors from 14_2_0_pre4

* First version of a reduced split FPGA2 project

* Changes so that each trackword has all layers

* Removing obsolete files

* Updates for new bin mask interface in VMStub memories

* Updates to VMStub memory implementation

* Fix issue with II=2 for test benches with new binned memory

* Fix CI script and adjust MemoryTemplateBinnedCM.h

* Remove some umused code

* Fix review comments to remove some hardcoded values

* Attempt to fix error in CI script

* Add comments

* Add missing start_bx.wcfg file

* Add some debug printout

* Multiple smaller fixes to address emulations vs HLS/vhdl differences for the reduced project

* Updates in WriteVHDLSyntax to write correct memory page size for the TPROJ and TPAR memories

* Restore script_IR.tcl to not run the negative modules

* Fix writing of tpar so TF memory properly filled

* Fix (kind of a hack) in the CompareMemPrintsFW.py to handle the overwrite used in full match memories

* Various fixes for BX alignment to get agreement for reduced project with emulation

* Various fixes for BX alignment to get agreement for reduced project with emulation

* Fix PR comments from A. Hart

* Fix intitialization logic

* Updates to 100 event reduced configuration

* Fix to use the hit mask for the mpar memory

* Correct calculation of number of stub words for writing TB memories

* Fixes for writing debug files

* Fixes to writing of debug files

* Handle overflow in VMSME memories in the comparison scripts

* Further fixes to get full agreement on 100 ttbar events. Fix latency to 11 in MatchProcessor to make latency the same in barrel and disks

* Address comments on PR 356

* Commit the 53fc560 commit of project_generation_script

* Fix changed obsolete constant name

* Fixes to TrackMerger after eliminating variable

* Pylint fixes from @aryd (#360)

* Trying to fix some of pylint warnings in the CI

* Correct indentation error

* Further indentation fixes...

* Fix more pylint warnings

* Fix more pylint warnings

* Fix more pylint warnings

* Fix more pylint warnings

* Fix more pylint warnings

* Fix more pylint warnings

* Fix more pylint warnings

* Fix more pylint warnings

* Fix more pylint warnings

* Fix more pylint warnings

* Fix more pylint warnings

* Fix more pylint warnings

* Fix more pylint warnings

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Co-authored-by: Anders Ryd <[email protected]>

---------

Co-authored-by: Anders Ryd <[email protected]>
Co-authored-by: Andrew Hart <[email protected]>
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