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- Corrected typo in module name for 1GB DDR for VC707 #28

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- Corrected typo in module name for 1GB DDR for VC707 #28

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2 changes: 1 addition & 1 deletion src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
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Expand Up @@ -108,7 +108,7 @@ class vc707mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox
val vc707mig1gbprj = """ {<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>vc707mig1gp</ModuleName>
<ModuleName>vc707mig1gb</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
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