Fixed Guard True branch

calyx/backend/src/firrtl.rs

@@ -262,7 +262,7 @@ fn get_guard_string(guard: &ir::Guard<ir::Nothing>) -> String {
             let g_str = get_guard_string(g);
             format!("not({g_str})")
         }
-        ir::Guard::True => String::from(""),
+        ir::Guard::True => String::from("UInt<1>(1)"),
         ir::Guard::CompOp(op, l, r) => {
             let l_str = get_port_string(&l.borrow(), false);
             let r_str = get_port_string(&r.borrow(), false);

tests/backend/firrtl/iterate-tutorial.expect

@@ -0,0 +1,273 @@
+circuit main:
+    module main:
+        input go: UInt<1>
+        input clk: Clock
+        input reset: UInt<1>
+        output done: UInt<1>
+        output mem_addr0: UInt<1>
+        output mem_write_data: UInt<32>
+        output mem_write_en: UInt<1>
+        input mem_read_data: UInt<32>
+        input mem_done: UInt<1>
+        done is invalid ; default initialization
+        done <= UInt(0)
+        mem_addr0 is invalid ; default initialization
+        mem_addr0 <= UInt(0)
+        mem_write_data is invalid ; default initialization
+        mem_write_data <= UInt(0)
+        mem_write_en is invalid ; default initialization
+        mem_write_en <= UInt(0)
+        ; COMPONENT START: main
+        inst val of std_reg_32
+        inst add of std_add_32
+        inst counter of std_reg_32
+        inst add2 of std_add_32
+        inst lt of std_lt_32
+        inst comb_reg of std_reg_1
+        inst fsm of std_reg_2
+        inst adder of std_add_2
+        inst ud0 of undef_1
+        inst ud1 of undef_1
+        inst signal_reg of std_reg_1
+        inst pd of std_reg_1
+        inst fsm0 of std_reg_2
+        inst pd0 of std_reg_1
+        inst fsm1 of std_reg_3
+        inst write_go of std_wire_1
+        inst write_done of std_wire_1
+        inst invoke0_go of std_wire_1
+        inst invoke0_done of std_wire_1
+        inst invoke2_go of std_wire_1
+        inst invoke2_done of std_wire_1
+        inst early_reset_static_seq_go of std_wire_1
+        inst early_reset_static_seq_done of std_wire_1
+        inst early_reset_cond00_go of std_wire_1
+        inst early_reset_cond00_done of std_wire_1
+        inst wrapper_early_reset_cond00_go of std_wire_1
+        inst wrapper_early_reset_cond00_done of std_wire_1
+        inst wrapper_early_reset_static_seq_go of std_wire_1
+        inst wrapper_early_reset_static_seq_done of std_wire_1
+        inst par0_go of std_wire_1
+        inst par0_done of std_wire_1
+        inst tdcc_go of std_wire_1
+        inst tdcc_done of std_wire_1
+        inst tdcc0_go of std_wire_1
+        inst tdcc0_done of std_wire_1
+        early_reset_cond00_go.in is invalid ; default initialization
+        early_reset_cond00_go.in <= UInt(0)
+        when wrapper_early_reset_cond00_go.out:
+            early_reset_cond00_go.in <= UInt(1)
+        when tdcc0_done.out:
+            done <= UInt(1)
+        when or(write_go.out, and(eq(fsm.out, UInt(0)), early_reset_static_seq_go.out)):
+            mem_addr0 <= UInt(0)
+        when write_go.out:
+            mem_write_en <= UInt(1)
+        when write_go.out:
+            mem_write_data <= val.out
+        fsm.write_en is invalid ; default initialization
+        fsm.write_en <= UInt(0)
+        when or(and(neq(fsm.out, UInt(1)), early_reset_static_seq_go.out), and(eq(fsm.out, UInt(1)), early_reset_static_seq_go.out)):
+            fsm.write_en <= UInt(1)
+        fsm.clk <= clk
+        fsm.reset <= reset
+        fsm.in is invalid ; default initialization
+        fsm.in <= UInt(0)
+        when and(neq(fsm.out, UInt(1)), early_reset_static_seq_go.out):
+            fsm.in <= adder.out
+        when and(eq(fsm.out, UInt(1)), early_reset_static_seq_go.out):
+            fsm.in <= UInt(0)
+        adder.left is invalid ; default initialization
+        adder.left <= UInt(0)
+        when early_reset_static_seq_go.out:
+            adder.left <= fsm.out
+        adder.right is invalid ; default initialization
+        adder.right <= UInt(0)
+        when early_reset_static_seq_go.out:
+            adder.right <= UInt(1)
+        invoke2_go.in is invalid ; default initialization
+        invoke2_go.in <= UInt(0)
+        when and(not(or(pd.out, invoke2_done.out)), par0_go.out):
+            invoke2_go.in <= UInt(1)
+        tdcc0_done.in is invalid ; default initialization
+        tdcc0_done.in <= UInt(0)
+        when eq(fsm1.out, UInt(4)):
+            tdcc0_done.in <= UInt(1)
+        add2.left is invalid ; default initialization
+        add2.left <= UInt(0)
+        when invoke2_go.out:
+            add2.left <= counter.out
+        add2.right is invalid ; default initialization
+        add2.right <= UInt(0)
+        when invoke2_go.out:
+            add2.right <= UInt(1)
+        comb_reg.write_en is invalid ; default initialization
+        comb_reg.write_en <= UInt(0)
+        when early_reset_cond00_go.out:
+            comb_reg.write_en <= UInt(1)
+        comb_reg.clk <= clk
+        comb_reg.reset <= reset
+        comb_reg.in is invalid ; default initialization
+        comb_reg.in <= UInt(0)
+        when early_reset_cond00_go.out:
+            comb_reg.in <= lt.out
+        write_go.in is invalid ; default initialization
+        write_go.in <= UInt(0)
+        when and(and(not(write_done.out), eq(fsm0.out, UInt(1))), tdcc_go.out):
+            write_go.in <= UInt(1)
+        early_reset_cond00_done.in <= ud1.out
+        val.write_en is invalid ; default initialization
+        val.write_en <= UInt(0)
+        when and(or(eq(fsm.out, UInt(0)), eq(fsm.out, UInt(1))), early_reset_static_seq_go.out):
+            val.write_en <= UInt(1)
+        val.clk <= clk
+        val.reset <= reset
+        val.in is invalid ; default initialization
+        val.in <= UInt(0)
+        when and(eq(fsm.out, UInt(0)), early_reset_static_seq_go.out):
+            val.in <= mem_read_data
+        when and(eq(fsm.out, UInt(1)), early_reset_static_seq_go.out):
+            val.in <= add.out
+        fsm1.write_en is invalid ; default initialization
+        fsm1.write_en <= UInt(0)
+        when or(or(or(or(or(or(eq(fsm1.out, UInt(4)), and(and(eq(fsm1.out, UInt(0)), invoke0_done.out), tdcc0_go.out)), and(and(eq(fsm1.out, UInt(1)), and(wrapper_early_reset_cond00_done.out, comb_reg.out)), tdcc0_go.out)), and(and(eq(fsm1.out, UInt(3)), and(wrapper_early_reset_cond00_done.out, comb_reg.out)), tdcc0_go.out)), and(and(eq(fsm1.out, UInt(2)), par0_done.out), tdcc0_go.out)), and(and(eq(fsm1.out, UInt(1)), and(wrapper_early_reset_cond00_done.out, not(comb_reg.out))), tdcc0_go.out)), and(and(eq(fsm1.out, UInt(3)), and(wrapper_early_reset_cond00_done.out, not(comb_reg.out))), tdcc0_go.out)):
+            fsm1.write_en <= UInt(1)
+        fsm1.clk <= clk
+        fsm1.reset <= reset
+        fsm1.in is invalid ; default initialization
+        fsm1.in <= UInt(0)
+        when or(and(and(eq(fsm1.out, UInt(1)), and(wrapper_early_reset_cond00_done.out, comb_reg.out)), tdcc0_go.out), and(and(eq(fsm1.out, UInt(3)), and(wrapper_early_reset_cond00_done.out, comb_reg.out)), tdcc0_go.out)):
+            fsm1.in <= UInt(2)
+        when or(and(and(eq(fsm1.out, UInt(1)), and(wrapper_early_reset_cond00_done.out, not(comb_reg.out))), tdcc0_go.out), and(and(eq(fsm1.out, UInt(3)), and(wrapper_early_reset_cond00_done.out, not(comb_reg.out))), tdcc0_go.out)):
+            fsm1.in <= UInt(4)
+        when eq(fsm1.out, UInt(4)):
+            fsm1.in <= UInt(0)
+        when and(and(eq(fsm1.out, UInt(0)), invoke0_done.out), tdcc0_go.out):
+            fsm1.in <= UInt(1)
+        when and(and(eq(fsm1.out, UInt(2)), par0_done.out), tdcc0_go.out):
+            fsm1.in <= UInt(3)
+        counter.write_en is invalid ; default initialization
+        counter.write_en <= UInt(0)
+        when or(invoke0_go.out, invoke2_go.out):
+            counter.write_en <= UInt(1)
+        counter.clk <= clk
+        counter.reset <= reset
+        counter.in is invalid ; default initialization
+        counter.in <= UInt(0)
+        when invoke0_go.out:
+            counter.in <= UInt(0)
+        when invoke2_go.out:
+            counter.in <= add2.out
+        invoke0_go.in is invalid ; default initialization
+        invoke0_go.in <= UInt(0)
+        when and(and(not(invoke0_done.out), eq(fsm1.out, UInt(0))), tdcc0_go.out):
+            invoke0_go.in <= UInt(1)
+        tdcc_go.in is invalid ; default initialization
+        tdcc_go.in <= UInt(0)
+        when and(not(or(pd0.out, tdcc_done.out)), par0_go.out):
+            tdcc_go.in <= UInt(1)
+        fsm0.write_en is invalid ; default initialization
+        fsm0.write_en <= UInt(0)
+        when or(or(eq(fsm0.out, UInt(2)), and(and(eq(fsm0.out, UInt(0)), wrapper_early_reset_static_seq_done.out), tdcc_go.out)), and(and(eq(fsm0.out, UInt(1)), write_done.out), tdcc_go.out)):
+            fsm0.write_en <= UInt(1)
+        fsm0.clk <= clk
+        fsm0.reset <= reset
+        fsm0.in is invalid ; default initialization
+        fsm0.in <= UInt(0)
+        when and(and(eq(fsm0.out, UInt(0)), wrapper_early_reset_static_seq_done.out), tdcc_go.out):
+            fsm0.in <= UInt(1)
+        when eq(fsm0.out, UInt(2)):
+            fsm0.in <= UInt(0)
+        when and(and(eq(fsm0.out, UInt(1)), write_done.out), tdcc_go.out):
+            fsm0.in <= UInt(2)
+        tdcc0_go.in <= go
+        write_done.in <= mem_done
+        wrapper_early_reset_static_seq_done.in is invalid ; default initialization
+        wrapper_early_reset_static_seq_done.in <= UInt(0)
+        when signal_reg.out:
+            wrapper_early_reset_static_seq_done.in <= UInt(1)
+        par0_done.in is invalid ; default initialization
+        par0_done.in <= UInt(0)
+        when and(pd.out, pd0.out):
+            par0_done.in <= UInt(1)
+        invoke0_done.in <= counter.done
+        early_reset_static_seq_go.in is invalid ; default initialization
+        early_reset_static_seq_go.in <= UInt(0)
+        when wrapper_early_reset_static_seq_go.out:
+            early_reset_static_seq_go.in <= UInt(1)
+        signal_reg.write_en is invalid ; default initialization
+        signal_reg.write_en <= UInt(0)
+        when or(or(signal_reg.out, and(and(and(UInt<1>(1), UInt<1>(1)), not(signal_reg.out)), wrapper_early_reset_cond00_go.out)), and(and(and(eq(fsm.out, UInt(1)), UInt<1>(1)), not(signal_reg.out)), wrapper_early_reset_static_seq_go.out)):
+            signal_reg.write_en <= UInt(1)
+        signal_reg.clk <= clk
+        signal_reg.reset <= reset
+        signal_reg.in is invalid ; default initialization
+        signal_reg.in <= UInt(0)
+        when or(and(and(and(UInt<1>(1), UInt<1>(1)), not(signal_reg.out)), wrapper_early_reset_cond00_go.out), and(and(and(eq(fsm.out, UInt(1)), UInt<1>(1)), not(signal_reg.out)), wrapper_early_reset_static_seq_go.out)):
+            signal_reg.in <= UInt(1)
+        when signal_reg.out:
+            signal_reg.in <= UInt(0)
+        invoke2_done.in <= counter.done
+        add.left is invalid ; default initialization
+        add.left <= UInt(0)
+        when and(eq(fsm.out, UInt(1)), early_reset_static_seq_go.out):
+            add.left <= val.out
+        add.right is invalid ; default initialization
+        add.right <= UInt(0)
+        when and(eq(fsm.out, UInt(1)), early_reset_static_seq_go.out):
+            add.right <= UInt(4)
+        pd.write_en is invalid ; default initialization
+        pd.write_en <= UInt(0)
+        when or(and(pd.out, pd0.out), and(invoke2_done.out, par0_go.out)):
+            pd.write_en <= UInt(1)
+        pd.clk <= clk
+        pd.reset <= reset
+        pd.in is invalid ; default initialization
+        pd.in <= UInt(0)
+        when and(invoke2_done.out, par0_go.out):
+            pd.in <= UInt(1)
+        when and(pd.out, pd0.out):
+            pd.in <= UInt(0)
+        pd0.write_en is invalid ; default initialization
+        pd0.write_en <= UInt(0)
+        when or(and(pd.out, pd0.out), and(tdcc_done.out, par0_go.out)):
+            pd0.write_en <= UInt(1)
+        pd0.clk <= clk
+        pd0.reset <= reset
+        pd0.in is invalid ; default initialization
+        pd0.in <= UInt(0)
+        when and(tdcc_done.out, par0_go.out):
+            pd0.in <= UInt(1)
+        when and(pd.out, pd0.out):
+            pd0.in <= UInt(0)
+        wrapper_early_reset_cond00_go.in is invalid ; default initialization
+        wrapper_early_reset_cond00_go.in <= UInt(0)
+        when or(and(and(not(wrapper_early_reset_cond00_done.out), eq(fsm1.out, UInt(1))), tdcc0_go.out), and(and(not(wrapper_early_reset_cond00_done.out), eq(fsm1.out, UInt(3))), tdcc0_go.out)):
+            wrapper_early_reset_cond00_go.in <= UInt(1)
+        wrapper_early_reset_cond00_done.in is invalid ; default initialization
+        wrapper_early_reset_cond00_done.in <= UInt(0)
+        when signal_reg.out:
+            wrapper_early_reset_cond00_done.in <= UInt(1)
+        early_reset_static_seq_done.in <= ud0.out
+        tdcc_done.in is invalid ; default initialization
+        tdcc_done.in <= UInt(0)
+        when eq(fsm0.out, UInt(2)):
+            tdcc_done.in <= UInt(1)
+        lt.left is invalid ; default initialization
+        lt.left <= UInt(0)
+        when early_reset_cond00_go.out:
+            lt.left <= counter.out
+        lt.right is invalid ; default initialization
+        lt.right <= UInt(0)
+        when early_reset_cond00_go.out:
+            lt.right <= UInt(8)
+        wrapper_early_reset_static_seq_go.in is invalid ; default initialization
+        wrapper_early_reset_static_seq_go.in <= UInt(0)
+        when and(and(not(wrapper_early_reset_static_seq_done.out), eq(fsm0.out, UInt(0))), tdcc_go.out):
+            wrapper_early_reset_static_seq_go.in <= UInt(1)
+        par0_go.in is invalid ; default initialization
+        par0_go.in <= UInt(0)
+        when and(and(not(par0_done.out), eq(fsm1.out, UInt(2))), tdcc0_go.out):
+            par0_go.in <= UInt(1)
+        ; COMPONENT END: main
+

tests/backend/firrtl/iterate-tutorial.futil

@@ -0,0 +1,84 @@
+// -b firrtl -p external-to-ref -p all
+import "primitives/core.futil";
+import "primitives/memories/comb.futil";
+
+component main() -> () {
+  cells {
+    @external(1) mem = comb_mem_d1(32, 1, 1);
+    val = std_reg(32);
+    add = std_add(32);
+
+    // ANCHOR: new_cells
+    counter = std_reg(32);
+    add2 = std_add(32);
+    lt = std_lt(32);
+    // ANCHOR_END: new_cells
+  }
+
+  wires {
+    group read {
+      mem.addr0 = 1'b0;
+      val.in = mem.read_data;
+      val.write_en = 1'b1;
+      read[done] = val.done;
+    }
+
+    group upd {
+      add.left = val.out;
+      add.right = 32'd4;
+      val.in = add.out;
+      val.write_en = 1'b1;
+      upd[done] = val.done;
+    }
+
+    group write {
+      mem.addr0 = 1'b0;
+      mem.write_en = 1'b1;
+      mem.write_data = val.out;
+      write[done] = mem.done;
+    }
+
+    // ANCHOR: init
+    group init {
+      counter.in = 32'd0;
+      counter.write_en = 1'b1;
+      init[done] = counter.done;
+    }
+    // ANCHOR_END: init
+
+    // ANCHOR: incr
+    group incr {
+      add2.left = counter.out;
+      add2.right = 32'd1;
+      counter.in = add2.out;
+      counter.write_en = 1'b1;
+      incr[done] = counter.done;
+    }
+    // ANCHOR_END: incr
+
+    // ANCHOR: cond
+    comb group cond {
+      lt.left = counter.out;
+      lt.right = 32'd8;
+    }
+    // ANCHOR_END: cond
+  }
+
+  // ANCHOR: control
+  control {
+    seq {
+      init;
+      while lt.out with cond {
+        par {
+          seq {
+            read;
+            upd;
+            write;
+          }
+          incr;
+        }
+      }
+    }
+  }
+  // ANCHOR_END: control
+}