A basic counter example for the ForgeFPGA dev kit, using the Pmod SSD dual seven segment display included in the kit.
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seven_seg_disp_ctrl_2d.v is from the ForgeFPGA modules library, copyright Renesas.
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input_reset_buf is from "AN-FG-015 ForgeFPGA Running String Example", copyright Renesas
cocotb testbench is the best, install cocotb and verilator to run it
Then either run python ./test_main.py or install pytest and use that to run them
- Better coverage in cocotb main testbench, curently 7 seg decoder is untested
- Make your own 7 seg decoder. Renesas's one has issues with bleeding and is bit undocumented
- See if I can get less warnings
- Actually add some timing constraints
- Added in timing_constraints.sdc but not yet working. Can't seem to find any working forgefpga examples.
- Use the "logic as clock" feature to run most logic off a slower clock, as can't reach 50MHz timing currently