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Refactor PRegSet. #178

Merged
merged 1 commit into from
Jun 6, 2024
Merged

Refactor PRegSet. #178

merged 1 commit into from
Jun 6, 2024

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numas13
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@numas13 numas13 commented Jun 1, 2024

The changes will make it easier to increase the number of physical registers and register classes in the future.

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@cfallin cfallin left a comment

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Thanks very much for this contribution! Two minor-nit comments below reflecting some preferences but nothing major; happy to have this generalization.

src/lib.rs Outdated
/// Splits the given register index into parts to access the internal bit array.
const fn split_index(reg: PReg) -> (usize, usize) {
let index = reg.index();
(index / Self::BITS, index % Self::BITS)
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It should be optimized via strength reduction but just to be sure in unoptimized builds: could we use shifts and masking here instead? AFAIK, BITS will always be a power of two.

src/lib.rs Outdated
let bits = self.bits.get_mut(self.cur)?;
if *bits != 0 {
let bit = bits.trailing_zeros();
*bits ^= 1 << bit;
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Can we stick with the &= !(1 << bit) form we had before, here? Equivalent in this case and not a huge deal either way, just a preference, but this form for me is slightly more clear in intent (clearing a bit, vs. XOR which I ordinarily see for flipping the bit).

The changes will make it easier to increase the number of physical
registers and register classes in the future.
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@cfallin cfallin left a comment

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Thanks!

@cfallin cfallin merged commit f4812a2 into bytecodealliance:main Jun 6, 2024
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2 participants