Releases: bsdevlin/vdf-fpga
Releases · bsdevlin/vdf-fpga
round 2 submission #3, 65MHz
round 2 submission #2, 61MHz
Functionally the same as submission #1, just different timing and placement constraints so able to acheive higher fmax, expected result (avg ns/square): 49.2ns/sq (3 clocks @ 61MHz)
round 2 submission #1, 50MHz
Expected result (avg ns/square): 60ns/sq (3 clocks @ 50MHz)