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Releases: bsdevlin/vdf-fpga

round 2 submission #3, 65MHz

31 Jan 07:50
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Functionally the same as submission #2, just different timing and placement constraints so able to achieve higher fmax, expected result (avg ns/square): ~46ns/sq (3 clocks @ 65MHz)

round 2 submission #2, 61MHz

31 Jan 06:39
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Functionally the same as submission #1, just different timing and placement constraints so able to acheive higher fmax, expected result (avg ns/square): 49.2ns/sq (3 clocks @ 61MHz)

round 2 submission #1, 50MHz

29 Jan 23:15
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Expected result (avg ns/square): 60ns/sq (3 clocks @ 50MHz)