cp15: optimize CP15_CleanAndFlushDCache #146
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asiekierka
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profi200
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Sorry for hijacking the PR a bit; apparently the behaviour of the write buffer drain is wrong, according to section 4.8 of ARM946-PRDC-000592 5.0 From that doc it seems the drain should happen immediately before every flush in inner_loop. Figured it'd be worth pinging here as the function in question is being modified in this PR. |
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The document is not exactly clear on whenever this is needed for both range and full cache operations. The examples only show the address variants (used in range flush). In this PR only the full cache flush got modified. |
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Appears to save up to ~5-6%. Can be benchmarked with https://github.com/asiekierka/nds-misc-tests/tree/main/cached-memory-performance
Not sure if this routine should be in ITCM or not, haven't tested the consequences - likewise the
cache.cequivalent.