Skip to content

Commit

Permalink
axi_hdmi_tx update for: ZedBoard, ZC706, ZC702, de10nano, ADRV9361-Z7…
Browse files Browse the repository at this point in the history 
…035 (analogdevicesinc#897)
  • Loading branch information
@PopPaul2021 @bkerler
PopPaul2021 authored and bkerler committed May 14, 2022
1 parent 9662a98 commit 7e9b22f
Show file tree
Hide file tree
Showing 10 changed files with 112 additions and 52 deletions.
34 changes: 25 additions & 9 deletions library/axi_hdmi_tx/axi_hdmi_tx.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -45,8 +45,9 @@ module axi_hdmi_tx #(

// hdmi interface

input hdmi_clk,
input reference_clk,
output hdmi_out_clk,
output vga_out_clk,

// 16-bit interface

Expand All @@ -62,6 +63,14 @@ module axi_hdmi_tx #(
output hdmi_24_vsync,
output hdmi_24_data_e,
output [23:0] hdmi_24_data,

// VGA interface

output vga_hsync,
output vga_vsync,
output [7:0] vga_red,
output [7:0] vga_green,
output [7:0] vga_blue,

// 36-bit interface

Expand Down Expand Up @@ -114,7 +123,7 @@ module axi_hdmi_tx #(

wire up_rstn;
wire up_clk;
wire hdmi_rst;
wire reference_rst;
wire vdma_rst;

// internal signals
Expand Down Expand Up @@ -160,6 +169,7 @@ module axi_hdmi_tx #(

assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
assign vga_out_clk = hdmi_out_clk;

// axi interface

Expand Down Expand Up @@ -195,8 +205,8 @@ module axi_hdmi_tx #(
// processor interface

up_hdmi_tx i_up (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_clk (reference_clk),
.hdmi_rst (reference_rst),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_ss_bypass (hdmi_ss_bypass_s),
.hdmi_srcsel (hdmi_srcsel_s),
Expand Down Expand Up @@ -255,11 +265,12 @@ module axi_hdmi_tx #(
// hdmi interface

axi_hdmi_tx_core #(
.INTERFACE(INTERFACE),
.CR_CB_N(CR_CB_N),
.EMBEDDED_SYNC(EMBEDDED_SYNC))
i_tx_core (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.reference_clk (reference_clk),
.reference_rst (reference_rst),
.hdmi_16_hsync (hdmi_16_hsync),
.hdmi_16_vsync (hdmi_16_vsync),
.hdmi_16_data_e (hdmi_16_data_e),
Expand All @@ -269,6 +280,11 @@ module axi_hdmi_tx #(
.hdmi_24_vsync (hdmi_24_vsync),
.hdmi_24_data_e (hdmi_24_data_e),
.hdmi_24_data (hdmi_24_data),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.vga_red(vga_red),
.vga_green(vga_green),
.vga_blue(vga_blue),
.hdmi_36_hsync (hdmi_36_hsync),
.hdmi_36_vsync (hdmi_36_vsync),
.hdmi_36_data_e (hdmi_36_data_e),
Expand Down Expand Up @@ -308,7 +324,7 @@ module axi_hdmi_tx #(
.SR (1'b0),
.D1 (~OUT_CLK_POLARITY),
.D2 (OUT_CLK_POLARITY),
.C (hdmi_clk),
.C (reference_clk),
.Q (hdmi_out_clk));
end
if (FPGA_TECHNOLOGY == INTEL_5SERIES) begin
Expand All @@ -321,7 +337,7 @@ module axi_hdmi_tx #(
.outclocken (1'b1),
.datain_h (~OUT_CLK_POLARITY),
.datain_l (OUT_CLK_POLARITY),
.outclock (hdmi_clk),
.outclock (reference_clk),
.oe_out (),
.dataout (hdmi_out_clk));
end
Expand All @@ -332,7 +348,7 @@ module axi_hdmi_tx #(
.CE (1'b1),
.D1 (~OUT_CLK_POLARITY),
.D2 (OUT_CLK_POLARITY),
.C (hdmi_clk),
.C (reference_clk),
.Q (hdmi_out_clk));
end
endgenerate
Expand Down
69 changes: 43 additions & 26 deletions library/axi_hdmi_tx/axi_hdmi_tx_core.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,12 +39,13 @@
module axi_hdmi_tx_core #(

parameter CR_CB_N = 0,
parameter EMBEDDED_SYNC = 0) (
parameter EMBEDDED_SYNC = 0,
parameter INTERFACE = "16_BIT") (

// hdmi interface

input hdmi_clk,
input hdmi_rst,
input reference_clk,
input reference_rst,

// 16-bit interface

Expand All @@ -61,6 +62,14 @@ module axi_hdmi_tx_core #(
output reg hdmi_24_data_e,
output reg [23:0] hdmi_24_data,

// VGA interface

output reg vga_hsync,
output reg vga_vsync,
output reg [7:0] vga_red,
output reg [7:0] vga_green,
output reg [7:0] vga_blue,

// 36-bit interface

output reg hdmi_36_hsync,
Expand Down Expand Up @@ -209,8 +218,8 @@ module axi_hdmi_tx_core #(

// status and enable

always @(posedge hdmi_clk) begin
if (hdmi_rst == 1'b1) begin
always @(posedge reference_clk) begin
if (reference_rst == 1'b1) begin
hdmi_status <= 1'b0;
hdmi_enable <= 1'b0;
end else begin
Expand All @@ -228,7 +237,7 @@ module axi_hdmi_tx_core #(

// hdmi counters

always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
if (hdmi_hs_count >= hdmi_hl_width_s) begin
hdmi_hs_count <= 0;
end else begin
Expand All @@ -245,8 +254,8 @@ module axi_hdmi_tx_core #(

// hdmi start of frame

always @(posedge hdmi_clk) begin
if (hdmi_rst == 1'b1) begin
always @(posedge reference_clk) begin
if (reference_rst == 1'b1) begin
hdmi_fs_toggle <= 1'b0;
hdmi_fs <= 1'b0;
end else begin
Expand All @@ -273,8 +282,8 @@ module axi_hdmi_tx_core #(

assign hdmi_fs_ret_s = hdmi_fs_ret_toggle_m2 ^ hdmi_fs_ret_toggle_m3;

always @(posedge hdmi_clk or posedge hdmi_rst) begin
if (hdmi_rst == 1'b1) begin
always @(posedge reference_clk or posedge reference_rst) begin
if (reference_rst == 1'b1) begin
hdmi_fs_ret_toggle_m1 <= 1'd0;
hdmi_fs_ret_toggle_m2 <= 1'd0;
hdmi_fs_ret_toggle_m3 <= 1'd0;
Expand All @@ -285,14 +294,14 @@ module axi_hdmi_tx_core #(
end
end

always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
hdmi_fs_ret <= hdmi_fs_ret_s;
hdmi_fs_waddr <= vdma_fs_waddr;
end

// hdmi sync signals

always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
if (EMBEDDED_SYNC == 1) begin
hdmi_hs <= 1'b0;
if (hdmi_hs_count <= hdmi_he_width_s) begin
Expand Down Expand Up @@ -333,8 +342,8 @@ module axi_hdmi_tx_core #(

assign hdmi_de_s = hdmi_hs_de & hdmi_vs_de;

always @(posedge hdmi_clk) begin
if (hdmi_rst == 1'b1) begin
always @(posedge reference_clk) begin
if (reference_rst == 1'b1) begin
hdmi_raddr <= 10'd0;
end else if (hdmi_fs == 1'b1) begin
hdmi_raddr <= {hdmi_fs_waddr, 1'b0};
Expand All @@ -346,7 +355,7 @@ module axi_hdmi_tx_core #(

// control and data pipe line

always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
hdmi_hs_d <= hdmi_hs;
hdmi_vs_d <= hdmi_vs;
hdmi_hs_de_d <= hdmi_hs_de;
Expand All @@ -368,18 +377,19 @@ module axi_hdmi_tx_core #(
assign hdmi_tpm_mismatch_s = (hdmi_data_2d_s == hdmi_tpm_data) ? 1'b0 : hdmi_de_2d;
assign hdmi_tpg_data_s = hdmi_tpm_data;

always @(posedge hdmi_clk) begin
if ((hdmi_rst == 1'b1) || (hdmi_fs_ret == 1'b1)) begin
always @(posedge reference_clk) begin
if ((reference_rst == 1'b1) || (hdmi_fs_ret == 1'b1)) begin
hdmi_tpm_data <= 'd0;
end else if (hdmi_de_2d == 1'b1) begin
hdmi_tpm_data <= hdmi_tpm_data + 1'b1;
end
hdmi_tpm_oos <= hdmi_tpm_mismatch_s;

end

// hdmi data select

always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
hdmi_hsync <= hdmi_hs_2d;
hdmi_vsync <= hdmi_vs_2d;
hdmi_hsync_data_e <= hdmi_hs_de_2d;
Expand All @@ -395,7 +405,7 @@ module axi_hdmi_tx_core #(

// Color space conversion bypass (RGB/YCbCr)

always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
if (hdmi_csc_bypass == 1'b1) begin
hdmi_24_csc_hsync <= hdmi_hsync;
hdmi_24_csc_vsync <= hdmi_vsync;
Expand All @@ -415,7 +425,7 @@ module axi_hdmi_tx_core #(

// hdmi clipping

always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
hdmi_clip_hs_d <= hdmi_24_csc_hsync;
hdmi_clip_vs_d <= hdmi_24_csc_vsync;
hdmi_clip_hs_de_d <= hdmi_24_csc_hsync_data_e;
Expand Down Expand Up @@ -455,7 +465,7 @@ module axi_hdmi_tx_core #(

// hdmi csc 16, 24 and 36 outputs

always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin

hdmi_36_hsync <= hdmi_clip_hs_d;
hdmi_36_vsync <= hdmi_clip_vs_d;
Expand All @@ -469,6 +479,13 @@ module axi_hdmi_tx_core #(
hdmi_24_data_e <= hdmi_clip_de_d;
hdmi_24_data <= hdmi_clip_data;

//VGA INTERFACE SIGNALS
vga_hsync <= hdmi_clip_hs_d;
vga_vsync <= hdmi_clip_vs_d;
vga_red <= hdmi_clip_data[23:16];
vga_green <= hdmi_clip_data[15:8];
vga_blue <= hdmi_clip_data[7:0];

hdmi_16_hsync <= hdmi_16_hsync_d;
hdmi_16_vsync <= hdmi_16_vsync_d;
hdmi_16_data_e <= hdmi_16_data_e_d;
Expand All @@ -494,7 +511,7 @@ module axi_hdmi_tx_core #(

// hdmi embedded sync

always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
hdmi_es_hs_de <= hdmi_16_hsync_data_e_d;
hdmi_es_vs_de <= hdmi_16_vsync_data_e_d;
if (hdmi_16_data_e_d == 1'b0) begin
Expand All @@ -516,15 +533,15 @@ module axi_hdmi_tx_core #(
.wea (vdma_wr),
.addra (vdma_waddr),
.dina (vdma_wdata),
.clkb (hdmi_clk),
.clkb (reference_clk),
.reb (1'b1),
.addrb (hdmi_raddr[9:1]),
.doutb (hdmi_rdata_s));

// color space coversion, RGB to CrYCb

ad_csc_RGB2CrYCb #(.DELAY_DATA_WIDTH(5)) i_csc_RGB2CrYCb (
.clk (hdmi_clk),
.clk (reference_clk),
.RGB_sync ({hdmi_hsync,
hdmi_vsync,
hdmi_hsync_data_e,
Expand All @@ -541,7 +558,7 @@ module axi_hdmi_tx_core #(
// sub sampling, 444 to 422

ad_ss_444to422 #(.DELAY_DATA_WIDTH(5), .CR_CB_N(CR_CB_N)) i_ss_444to422 (
.clk (hdmi_clk),
.clk (reference_clk),
.s444_de (hdmi_clip_de_d),
.s444_sync ({hdmi_clip_hs_d,
hdmi_clip_vs_d,
Expand All @@ -559,7 +576,7 @@ module axi_hdmi_tx_core #(
// embedded sync

axi_hdmi_tx_es #(.DATA_WIDTH(16)) i_es (
.hdmi_clk (hdmi_clk),
.reference_clk (reference_clk),
.hdmi_hs_de (hdmi_es_hs_de),
.hdmi_vs_de (hdmi_es_vs_de),
.hdmi_data_de (hdmi_es_data),
Expand Down
4 changes: 2 additions & 2 deletions library/axi_hdmi_tx/axi_hdmi_tx_es.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,7 @@ module axi_hdmi_tx_es #(

// hdmi interface

input hdmi_clk,
input reference_clk,
input hdmi_hs_de,
input hdmi_vs_de,
input [(DATA_WIDTH-1):0] hdmi_data_de,
Expand Down Expand Up @@ -73,7 +73,7 @@ module axi_hdmi_tx_es #(
assign hdmi_sav_s = (hdmi_vs_de == 1) ? {BYTE_WIDTH{8'h80}} : {BYTE_WIDTH{8'hab}};
assign hdmi_eav_s = (hdmi_vs_de == 1) ? {BYTE_WIDTH{8'h9d}} : {BYTE_WIDTH{8'hb6}};

always @(posedge hdmi_clk) begin
always @(posedge reference_clk) begin
hdmi_hs_de_d <= hdmi_hs_de;
case ({hdmi_hs_de_4d, hdmi_hs_de_3d, hdmi_hs_de_2d,
hdmi_hs_de_d, hdmi_hs_de})
Expand Down
Loading

0 comments on commit 7e9b22f

Please sign in to comment.