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Bump vivado to 2025.2 #1224

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2 changes: 1 addition & 1 deletion .github/scripts/with_vivado.sh
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Expand Up @@ -7,7 +7,7 @@ set -euo pipefail
IFS=$'\n\t'

# Get Vivado environment in scope
source /opt/tools/Xilinx/VivadoEnterprise/Vivado/2022.1/settings64.sh
source /opt/tools/Xilinx/2025.2/Vivado/settings64.sh

# Work around https://support.xilinx.com/s/question/0D52E000079NURRSA4/synthesis-failed-abnormal-termination-tcmalloc-large-allocation?language=en_US
export LD_PRELOAD=/lib/x86_64-linux-gnu/libudev.so.1
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2 changes: 1 addition & 1 deletion .github/workflows/ci.yml
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Expand Up @@ -491,7 +491,7 @@ jobs:
image: ghcr.io/clash-lang/nixos-bittide-hardware:2025-12-17
volumes:
- /opt/tools:/opt/tools
options: --init --mac-address="6c:5a:b0:6c:13:0b" --memory=15g
options: --init --mac-address="28:87:ba:f3:e0:77" --memory=15g

steps:
- name: Checkout
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4 changes: 2 additions & 2 deletions bittide/src/Clash/Cores/Xilinx/Gth/Internal.hs
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Expand Up @@ -304,7 +304,7 @@ xilinxGthUserClockNetworkTx clkIn rstIn = (usrclk_out, usrclk2_out, pack <$> tx_
, unPort @(Port "gtwiz_userclk_tx_active_out" user2 Bit) -> tx_active_out
) =
inst
(instConfig "gtwizard_ultrascale_v1_7_13_gtwiz_userclk_tx")
(instConfig "gtwizard_ultrascale_v1_7_22_gtwiz_userclk_tx")
(Param @"P_FREQ_RATIO_USRCLK_TO_USRCLK2" (2 :: Integer))
(ClockPort @"gtwiz_userclk_tx_srcclk_in" clkIn)
(ResetPort @"gtwiz_userclk_tx_reset_in" @ActiveHigh rstIn)
Expand All @@ -323,7 +323,7 @@ xilinxGthUserClockNetworkRx clkIn rstIn = (usrclk_out, usrclk2_out, pack <$> rx_
, unPort @(Port "gtwiz_userclk_rx_active_out" user2 Bit) -> rx_active_out
) =
inst
(instConfig "gtwizard_ultrascale_v1_7_13_gtwiz_userclk_rx")
(instConfig "gtwizard_ultrascale_v1_7_22_gtwiz_userclk_rx")
(Param @"P_FREQ_RATIO_USRCLK_TO_USRCLK2" (2 :: Integer))
(ClockPort @"gtwiz_userclk_rx_srcclk_in" clkIn)
(ResetPort @"gtwiz_userclk_rx_reset_in" @ActiveHigh rstIn)
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